From 438978cf4a68a0f30f202b961b895dc9ceed5188 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 26 Feb 2020 11:11:38 +0100 Subject: [PATCH] ARM: zynq: Do not include full zynq-7000.dtsi to cse-nor configuration There is no real need to include full DT when only some nodes are enough to use. It will save some space. Retested with FSBL for initial SoC setup. SPL didn't work. Signed-off-by: Michal Simek --- arch/arm/dts/zynq-cse-nor.dts | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/arch/arm/dts/zynq-cse-nor.dts b/arch/arm/dts/zynq-cse-nor.dts index 9710abadcf..4030851eb3 100644 --- a/arch/arm/dts/zynq-cse-nor.dts +++ b/arch/arm/dts/zynq-cse-nor.dts @@ -5,7 +5,6 @@ * Copyright (C) 2018 Xilinx, Inc. */ /dts-v1/; -#include "zynq-7000.dtsi" / { #address-cells = <1>; @@ -33,27 +32,21 @@ }; amba: amba { + u-boot,dm-pre-reloc; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - interrupt-parent = <&intc>; ranges; - intc: interrupt-controller@f8f01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0xF8F01000 0x1000>, - <0xF8F00100 0x100>; - }; - slcr: slcr@f8000000 { + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { + u-boot,dm-pre-reloc; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; clock-output-names = "armpll", "ddrpll", -- 2.39.5