From 355dc3d4deacf73a3d354682bcda454e6d13ed66 Mon Sep 17 00:00:00 2001 From: Jay Buddhabhatti Date: Mon, 23 Jan 2023 23:32:35 -0800 Subject: [PATCH] fix(versal-net): populate gic v3 rdist data statically Currently gicv3_rdistif_probe() is called per CPU. In case of maxcpus=1, only 1 core is initialized and gicr_base_addrs initialized for CPU 0 only. Because of this assertion is raised during Linux system suspend. During Linux suspend, platform callback saves GIC v3 state which internally invokes arm_gicv3_distif_pre_save(). This function tries to use gicr_base for all CPUs. Since GICR base address for secondary CPUs are not initialized, it raises assertion. To fix the issue, populate GIC v3 rdist data statically (similar to Versal) instead of dynamically initializing GIC v3 rdist per CPU. Signed-off-by: Jay Buddhabhatti Change-Id: I98c97c03e451d05f4ebac358e197617ab9d9b71f --- plat/xilinx/versal_net/versal_net_gicv3.c | 37 ++--------------------- 1 file changed, 2 insertions(+), 35 deletions(-) diff --git a/plat/xilinx/versal_net/versal_net_gicv3.c b/plat/xilinx/versal_net/versal_net_gicv3.c index b7ac6abbc..1d45a5887 100644 --- a/plat/xilinx/versal_net/versal_net_gicv3.c +++ b/plat/xilinx/versal_net/versal_net_gicv3.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. - * Copyright (C) 2022, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -30,14 +30,6 @@ /* The GICv3 driver only needs to be initialized in EL3 */ static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; -static const uintptr_t gicr_base_addrs[2] = { - PLAT_VERSAL_NET_GICR_BASE, /* GICR Base address of the primary CPU */ - 0U /* Zero Termination */ -}; - -/* List of zero terminated GICR frame addresses which CPUs will probe */ -static const uintptr_t *gicr_frames; - static const interrupt_prop_t versal_net_interrupt_props[] = { PLAT_VERSAL_NET_G1S_IRQ_PROPS(INTR_GROUP1S), PLAT_VERSAL_NET_G0_IRQ_PROPS(INTR_GROUP0) @@ -72,7 +64,7 @@ static uint32_t versal_net_gicv3_mpidr_hash(u_register_t mpidr) static const gicv3_driver_data_t versal_net_gic_data __unused = { .gicd_base = PLAT_VERSAL_NET_GICD_BASE, - .gicr_base = 0U, + .gicr_base = PLAT_VERSAL_NET_GICR_BASE, .interrupt_props = versal_net_interrupt_props, .interrupt_props_num = ARRAY_SIZE(versal_net_interrupt_props), .rdistif_num = PLATFORM_CORE_COUNT, @@ -90,12 +82,6 @@ void __init plat_versal_net_gic_driver_init(void) */ #if IMAGE_BL31 gicv3_driver_init(&versal_net_gic_data); - gicr_frames = gicr_base_addrs; - - if (gicv3_rdistif_probe(gicr_frames[0]) == -1) { - ERROR("No GICR base frame found for Primary CPU\n"); - panic(); - } #endif } @@ -131,25 +117,6 @@ void plat_versal_net_gic_cpuif_disable(void) *****************************************************************************/ void plat_versal_net_gic_pcpu_init(void) { - int32_t result; - const uintptr_t *plat_gicr_frames = gicr_frames; - - do { - result = gicv3_rdistif_probe(*plat_gicr_frames); - - /* If the probe is successful, no need to proceed further */ - if (result == 0) { - break; - } - - plat_gicr_frames++; - } while (*plat_gicr_frames != 0U); - - if (result == -1) { - ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr()); - panic(); - } - gicv3_rdistif_init(plat_my_core_pos()); } -- 2.39.5