From 2c3b76ce7b9e36e5c8be3c454110e070a20332ca Mon Sep 17 00:00:00 2001
From: Louis Mayencourt <louis.mayencourt@arm.com>
Date: Tue, 9 Apr 2019 14:11:06 +0100
Subject: [PATCH] DSU: Small fix and reformat on errata framework

Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
---
 include/lib/cpus/aarch64/dsu_def.h | 18 ++++++++----
 lib/cpus/aarch64/dsu_helpers.S     | 44 +++++++++++++++---------------
 2 files changed, 34 insertions(+), 28 deletions(-)

diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index b7ba28a4a..4ec64eee3 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -10,23 +10,29 @@
 #include <lib/utils_def.h>
 
 /********************************************************************
- * DSU control registers definitions				    *
+ * DSU Cluster Configuration registers definitions
  ********************************************************************/
 #define CLUSTERCFR_EL1		S3_0_C15_C3_0
-#define CLUSTERIDR_EL1		S3_0_C15_C3_1
-#define CLUSTERACTLR_EL1	S3_0_C15_C3_3
+
+#define CLUSTERCFR_ACP_SHIFT	U(11)
 
 /********************************************************************
- * DSU control registers bit fields				    *
+ * DSU Cluster Main Revision ID registers definitions
  ********************************************************************/
+#define CLUSTERIDR_EL1		S3_0_C15_C3_1
+
 #define CLUSTERIDR_REV_SHIFT	U(0)
 #define CLUSTERIDR_REV_BITS	U(4)
 #define CLUSTERIDR_VAR_SHIFT	U(4)
 #define CLUSTERIDR_VAR_BITS	U(4)
-#define CLUSTERCFR_ACP_SHIFT	U(11)
 
 /********************************************************************
- * Masks applied for DSU errata workarounds			    *
+ * DSU Cluster Auxiliary Control registers definitions
+ ********************************************************************/
+#define CLUSTERACTLR_EL1	S3_0_C15_C3_3
+
+/********************************************************************
+ * Masks applied for DSU errata workarounds
  ********************************************************************/
 #define DSU_ERRATA_936184_MASK	(U(0x3) << 15)
 
diff --git a/lib/cpus/aarch64/dsu_helpers.S b/lib/cpus/aarch64/dsu_helpers.S
index eb84daacf..29870a4d3 100644
--- a/lib/cpus/aarch64/dsu_helpers.S
+++ b/lib/cpus/aarch64/dsu_helpers.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,20 +8,20 @@
 #include <dsu_def.h>
 #include <lib/cpus/errata_report.h>
 
-/* -----------------------------------------------------------------------
- * DSU erratum 936184 check function
- * Checks the DSU variant, revision and configuration to determine if
- * the erratum applies. Erratum applies if ACP interface is present
- * in the DSU and revision-variant < r2p0.
- *
- * The erratum was fixed in r2p0.
- *
- * This function is called from both assembly and C environment. So it
- * follows AAPCS.
- *
- * Clobbers: x0-x3
- * -----------------------------------------------------------------------
- */
+	/* -----------------------------------------------------------------------
+	 * DSU erratum 936184 check function
+	 * Checks the DSU variant, revision and configuration to determine if
+	 * the erratum applies. Erratum applies if ACP interface is present
+	 * in the DSU and revision-variant < r2p0.
+	 *
+	 * The erratum was fixed in r2p0.
+	 *
+	 * This function is called from both assembly and C environment. So it
+	 * follows AAPCS.
+	 *
+	 * Clobbers: x0-x3
+	 * -----------------------------------------------------------------------
+	 */
 	.globl	check_errata_dsu_936184
 	.globl	errata_dsu_936184_wa
 
@@ -41,19 +41,19 @@ func check_errata_dsu_936184
 	/* DSU variant and revision bitfields in CLUSTERIDR are adjacent */
 	ubfx	x0, x1, #CLUSTERIDR_REV_SHIFT,\
 			#(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS)
-	mov	x1, #(0x2 << CLUSTERIDR_REV_BITS)
+	mov	x1, #(0x2 << CLUSTERIDR_VAR_SHIFT)
 	cmp	x0, x1
 	csel	x0, x2, x3, hs
 1:
 	ret
 endfunc check_errata_dsu_936184
 
-/* --------------------------------------------------
- * Errata Workaround for DSU erratum #936184.
- *
- * Can clobber only: x0-x17
- * --------------------------------------------------
- */
+	/* --------------------------------------------------
+	 * Errata Workaround for DSU erratum #936184.
+	 *
+	 * Can clobber only: x0-x17
+	 * --------------------------------------------------
+	 */
 func errata_dsu_936184_wa
 	mov	x17, x30
 	bl	check_errata_dsu_936184
-- 
2.39.5