From 2537f0725ee7d8f46bef3e5b49134419b5c3367b Mon Sep 17 00:00:00 2001 From: Akshay Belsare Date: Wed, 15 Feb 2023 10:49:52 +0530 Subject: [PATCH] fix(zynqmp): with DEBUG=1 move bl31 to DDR range Due to size constraints in OCM memory range keeping the bl31 with DEBUG=1 overlaps with the memory range from other Firmware thus affecting the bootflow on target. bl31 binary can not be placed in OCM memory range when built with DEBUG=1. With DEBUG=1, by default bl31 is moved to DDR memory range 0x1000-0x7FFFF. The user can provide a custom DDR memory range during build time using the build parameters ZYNQMP_ATF_MEM_BASE and ZYNQMP_ATF_MEM_SIZE. Change-Id: I167d5eadbae7c6d3ec9b32f494b0b1a819bea5b0 Signed-off-by: Akshay Belsare --- docs/plat/xilinx-zynqmp.rst | 15 +++++++++++++++ plat/xilinx/zynqmp/include/platform_def.h | 4 ++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/docs/plat/xilinx-zynqmp.rst b/docs/plat/xilinx-zynqmp.rst index af1cb22c5..bc6bb3405 100644 --- a/docs/plat/xilinx-zynqmp.rst +++ b/docs/plat/xilinx-zynqmp.rst @@ -41,6 +41,21 @@ ZynqMP platform specific build options - ``cadence``, ``cadence0``: Cadence UART 0 - ``cadence1`` : Cadence UART 1 +ZynqMP Debug behavior +--------------------- + +With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range +due to size constraints. +For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location +of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. + +If the user wants to move the bl31 to a different DDR location, user can provide +the DDR address location in the build command as follows, + +make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ + ZYNQMP_ATF_MEM_BASE= ZYNQMP_ATF_MEM_SIZE= bl31 + + FSBL->TF-A Parameter Passing ---------------------------- diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h index fbf01ca77..ffed0eee7 100644 --- a/plat/xilinx/zynqmp/include/platform_def.h +++ b/plat/xilinx/zynqmp/include/platform_def.h @@ -40,8 +40,8 @@ # define BL31_BASE U(0xfffea000) # define BL31_LIMIT U(0x100000000) #else -# define BL31_BASE U(0xfffe5000) -# define BL31_LIMIT U(0x100000000) +# define BL31_BASE U(0x1000) +# define BL31_LIMIT U(0x7ffff) #endif #else # define BL31_BASE (ZYNQMP_ATF_MEM_BASE) -- 2.39.5