From 1fa2b63116386ad453f2218d188dd80fcd149ad6 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 2 Feb 2021 13:33:22 +0100 Subject: [PATCH] xilinx: common: Fix CONFIG_XILINX_OF_BOARD_DTB_ADDR handling for ZynqMP Fix bug introduced by commit listed below. It is for cases where Versal or ZynqMP don't have DDR mapped. Later SPL was also excluded by commit 2d4d81763409 ("xilinx: common: Do not touch CONFIG_XILINX_OF_BOARD_DTB_ADDR in SPL"). Fixes: ed6ab9472914 ("xilinx: common: Change macro handling in board_fdt_blob_setup()") Signed-off-by: Michal Simek --- board/xilinx/common/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index df19aeadd0..1a259c5785 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -326,7 +326,7 @@ void *board_fdt_blob_setup(void) if (!IS_ENABLED(CONFIG_SPL_BUILD) && !IS_ENABLED(CONFIG_VERSAL_NO_DDR) && - !IS_ENABLED(CONFIG_VERSAL_NO_DDR)) { + !IS_ENABLED(CONFIG_ZYNQMP_NO_DDR)) { fdt_blob = (void *)CONFIG_XILINX_OF_BOARD_DTB_ADDR; if (fdt_magic(fdt_blob) == FDT_MAGIC) -- 2.39.5