From 0d9af20e5764f614a188b6c6bbe580aff5d464c7 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Tue, 17 May 2016 15:31:05 +0100 Subject: [PATCH] MIPS: smp-cps: Clear Status IPL field when using EIC When using an external interrupt controller (EIC) the interrupt mask bits in the cop0 Status register are reused for the Interrupt Priority Level, and any interrupts with a priority lower than the field will be ignored. Clear the field to 0 by default such that all interrupts are serviced. Signed-off-by: Paul Burton Reviewed-by: Matt Redfearn Tested-by: Matt Redfearn Cc: Qais Yousef Cc: Thomas Gleixner Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13273/ Signed-off-by: Ralf Baechle --- arch/mips/kernel/smp-cps.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index 1061bd2e7e9ca..4ed36f288d646 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -359,8 +359,12 @@ static void cps_init_secondary(void) BUG_ON(ident != mips_cm_vp_id(smp_processor_id())); } - change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 | - STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7); + if (cpu_has_veic) + clear_c0_status(ST0_IM); + else + change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | + STATUSF_IP4 | STATUSF_IP5 | + STATUSF_IP6 | STATUSF_IP7); } static void cps_smp_finish(void) -- 2.39.5