]> git.baikalelectronics.ru Git - uboot.git/commit
riscv: Clear pending interrupts before enabling IPIs
authorSean Anderson <seanga2@gmail.com>
Wed, 24 Jun 2020 10:41:17 +0000 (06:41 -0400)
committerAndes <uboot@andestech.com>
Wed, 1 Jul 2020 07:01:21 +0000 (15:01 +0800)
commit7126b4ea19b65df7d4380fa58c54aa8c7ad3ef9c
tree15f2ed2668c54a0f7dc594d8a555890a817434f9
parentd3c245dc950d4db29e5355958846b9427cdb21d6
riscv: Clear pending interrupts before enabling IPIs

On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
arch/riscv/cpu/start.S