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(parent: cd2877f) | patch
ARM: dts: bcm2837: Add the missing L1/L2 cache information
authorRichard Schleich <rs@noreya.tech>
Sat, 18 Dec 2021 20:00:09 +0000 (21:00 +0100)
committerFlorian Fainelli <f.fainelli@gmail.com>
Tue, 1 Feb 2022 00:27:51 +0000 (16:27 -0800)
commit6f6f2c7d8b4e32feab10c4610725af682c5d081c
tree11a3d780a84c074f444f5630c8d5b2e874064e28tree | snapshot
parentcd2877fb4c572753183a5161dc42e79f9843d995commit | diff
ARM: dts: bcm2837: Add the missing L1/L2 cache information

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
[florian: Align and remove comments matching property values]
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
arch/arm/boot/dts/bcm2837.dtsi diff | blob | history
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