]> git.baikalelectronics.ru Git - kernel.git/commit
drm/amd/display: Pass the new context into disable OTG WA
authorNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Fri, 6 May 2022 16:56:38 +0000 (12:56 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jun 2022 19:56:48 +0000 (15:56 -0400)
commit692bc9afb6316c1083145832ed3374dded8deb52
tree0c8807c25f0724995e608fc128f234e121c02d55
parenta51ccc77932e9709024761298925a5b96a63d5fd
drm/amd/display: Pass the new context into disable OTG WA

[Why]
When enabling an HPO stream for the first time after having previously
enabled a DIO stream there may be lingering DIO FIFO errors even though
the DIO is no longer enabled.

These can cause display clock change to hang if we don't apply the
OTG disable workaround since the ramping logic is tied to OTG on.

[How]
The workaround wasn't being applied in the sequence of:

1 DIO stream
0 streams
1 HPO stream

because current_state has no stream or planes in its context - and
it's only swapped after optimize has finished.

We should be using the incoming context instead to determine whether
this logic is needed or not.

Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Jasdeep Dhillon <jdhillon@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h