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i2c: piix4: Enable EFCH MMIO for Family 17h+
authorTerry Bowman <terry.bowman@amd.com>
Wed, 9 Feb 2022 17:27:17 +0000 (11:27 -0600)
committerWolfram Sang <wsa@kernel.org>
Fri, 11 Feb 2022 14:38:23 +0000 (15:38 +0100)
commit67a44e78eb5c37318e09c221008d7527b5ab9b06
treeb796a0e0bc0b83c30616562814200e58a4782727tree | snapshot
parente8c6f85c0da777c866cd53a117ef7cf0ad59d100commit | diff
i2c: piix4: Enable EFCH MMIO for Family 17h+

Enable EFCH MMIO using check for SMBus PCI revision ID value 0x51 or
greater. This PCI revision ID check will enable family 17h and future
AMD processors with the same EFCH SMBus controller HW.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
drivers/i2c/busses/i2c-piix4.c diff | blob | history
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