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(parent: 80ae592) | patch
riscv: cpu: fu740: clear feature disable CSR
authorGreen Wan <green.wan@sifive.com>
Mon, 3 May 2021 06:23:05 +0000 (23:23 -0700)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Wed, 5 May 2021 08:11:27 +0000 (16:11 +0800)
commit2a8b450b791a705d92266ae8a080f21fbc65d8a5
tree4447ce691bef6dd9d3bb165a031d42dfe5e50442tree | snapshot
parent80ae592f773aab9a0472f9e846e0a863a6ce5506commit | diff
riscv: cpu: fu740: clear feature disable CSR

Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
arch/riscv/cpu/fu540/spl.c diff | blob | history
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