MIPS: Avoid pipeline stalls on some MIPS32R2 cores.

MIPS: Avoid pipeline stalls on some MIPS32R2 cores.

The architecture specification says that an EHB instruction is
needed to avoid a hazard when writing TLB entries. However, some
cores do not have this hazard, and thus the EHB instruction causes
a costly pipeline stall. Detect these cores and do not use the EHB
instruction.

Signed-off-by: Steven J. Hill <sjhill@mips.com>