Stephen Carlson [Fri, 10 Mar 2023 19:07:13 +0000 (11:07 -0800)]
cmd: pci: Add command to set MPS of all PCIe devices
Enable tuning of the PCI Express MPS (Maximum Payload Size) of
each device. The Maximum Read Request Size is not altered.
The SAFE method uses the largest MPS value supported by all devices in the
system for each device. This method is the same algorithm as used by Linux
pci=pcie_bus_safe.
The PEER2PEER method sets all devices to the minimal (128 byte) MPS, which
allows hot plug of devices later that might only support the minimum size,
and ensures compatibility of DMA between two devices on the bus.
Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com>
Rasmus Villemoes [Fri, 10 Mar 2023 10:58:03 +0000 (11:58 +0100)]
sysinfo: gpio: fix loop over DT "revisions" array
There can certainly be a lot more elements in the "revisions" (and
"names") arrays than there are gpios used to form the trinary number
we're searching for; we simply don't know the array size up-front.
Nor do we need to, because the loop body already knows to recognize
-EOVERFLOW as "not that many elements present" (and we have a test
that specifically ensures that dev_read_u32_index() returns exactly
that). So just drop the i < priv->gpio_num condition.
While in here, fix the weird placement of the default: keyword.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <sean.anderson@seco.com>
Instead of calling env_get(from) up to three times, just do it once,
computing the value we will put into 'to' and error out if that is
NULL (i.e. no 'from' variable and no default provided).
No functional change.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Mon, 27 Feb 2023 19:56:31 +0000 (20:56 +0100)]
image: Fix potentially uninitialized data variable
In case fitImage support is disabled, and image_locate_script() is
passed a fitImage, then the 'data' variable is used uninitialized.
Drop into the default: branch of the switch-case statement and do
not return the uninitialized data, and do not modify the return
pointer either, just print an error message.
Reported by clang build:
"
$ make HOSTCC=clang CC=clang KCFLAGS=-Werror sandbox64_defconfig && make HOSTCC=clang CC=clang KCFLAGS=-Werror
...
boot/image-board.c:1006:7: error: variable 'data' is used uninitialized whenever switch case is taken [-Werror,-Wsometimes-uninitialized]
case IMAGE_FORMAT_LEGACY:
^~~~~~~~~~~~~~~~~~~
include/image.h:608:29: note: expanded from macro 'IMAGE_FORMAT_LEGACY'
^~~~
boot/image-board.c:1128:19: note: uninitialized use occurs here
*datap = (char *)data;
^~~~
boot/image-board.c:1001:11: note: initialize the variable 'data' to silence this warning
u32 *data;
^
= NULL
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Mon, 6 Mar 2023 14:53:54 +0000 (15:53 +0100)]
arm64: imx8mm: imx8mn: imx8mp: Drop FEC GPR[1] board workaround
The FEC interface mode is now configured in common board_interface_eth_init()
and called by FEC MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Marek Vasut [Mon, 6 Mar 2023 14:53:53 +0000 (15:53 +0100)]
arm64: imx8mp: Drop EQoS GPR[1] board workaround
The EQoS interface mode is now configured in common board_interface_eth_init()
and called by EQoS MAC driver when appropriate. Drop the board side duplicates
if the same functionality.
Marek Vasut [Mon, 6 Mar 2023 14:53:52 +0000 (15:53 +0100)]
arm64: dts: imx8mp: Drop EQoS clock workaround
The assigned-clock no longer have to be dropped, the clock are now
defined in clk-imx8mp.c and used by DWMAC driver to configure the
DWMAC clock. Drop the workarounds from U-Boot specific DT extras.
Emanuele Ghidoli [Thu, 16 Feb 2023 11:31:15 +0000 (12:31 +0100)]
configs: verdin-imx8mp: Fix wrong early malloc() heap size
Set, previously unset, CONFIG_SPL_SYS_MALLOC_F_LEN to 0x4000 whose
default value is 0x10000.
Early malloc() uses CRAM_S at 0x184000 (CFG_MALLOC_F_ADDR), this ram
area end at 0x188000.
Rasmus Villemoes [Wed, 22 Mar 2023 14:42:05 +0000 (15:42 +0100)]
ARM: imx: imx8mp: fix enable_i2c_clk
In order for i2c_num==4 and 5 to stay invalid for non-imx8mp SOCs, the
i2c_ccgr[] array must be sized by the number of initializers present,
not with a hard-coded 6 which would implicitly initialize the last two
elements with zeroes.
Also, the bounds check is off-by-one.
Fixes: c027e1f191a5 "ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP" Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Marek Vasut [Mon, 6 Mar 2023 14:53:51 +0000 (15:53 +0100)]
net: fec_mxc: Add board_interface_eth_init() for i.MX8M Mini/Nano/Plus
Implement common board_interface_eth_init() and call it from the FEC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Mini/Nano/Plus FEC and supersedes the current board-side
configuration of the same IOMUX GPR[1] duplicated in the board files.
Marek Vasut [Mon, 6 Mar 2023 14:53:50 +0000 (15:53 +0100)]
net: fec_mxc: Add ref clock setup support for i.MX8M Mini/Nano/Plus
The FEC ref clock frequency on i.MX8M Mini/Nano/Plus was so far configured
via ad-hoc board code. Replace that with DM clock clk_set_rate() instead.
This way, the driver claims all its required clock and sets the ref clock
rate, without any need of architecture specific register fiddling.
Marek Vasut [Mon, 6 Mar 2023 14:53:49 +0000 (15:53 +0100)]
net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 6 Mar 2023 14:53:48 +0000 (15:53 +0100)]
net: dwc_eth_qos: Add i.MX8M Plus RMII support
With DM clock support in place, it is easy to add RMII support into the
MAC driver. The RMII cannot operate at 1000 Mbps and at 100 and 10 Mbps
the clock frequency is 50 MHz and 5 MHz instead of 25 MHz and 2.5 MHz.
The board DT requires the following adjustments to EQoS node:
phy-mode = "rmii";
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>;
Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 6 Mar 2023 14:53:47 +0000 (15:53 +0100)]
net: dwc_eth_qos: Add DM CLK support for i.MX8M Plus
The DWMAC clock in i.MX8M Plus were so far configured via ad-hoc
architecture code. Replace that with DM clock instead. This way,
the driver claims all its required clock, enables and disables
them, and even gets the CSR clock rate and sets the TX clock rate,
without any need of architecture specific register fiddling. Drop
the architecture specific code while at it too.
The adjustment here is modeled after STM32MP15xx clock handling
in this driver.
Marek Vasut [Mon, 6 Mar 2023 14:53:46 +0000 (15:53 +0100)]
net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC
The driver currently only waits for DMA_MODE SWR bit to clear itself.
This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset
before IOMUX GPR[1] content is latched into the MAC and used. Without
the proper reset, the i.MX8M Plus MAC variant does not take the value
in IOMUX GPR[1] into account, which makes it impossible e.g. to switch
interface mode from RGMII to any other.
Since proper reset is desired in general to put the block into defined
state, always assert the DMA_MODE SWR bit before waiting for the bit
to clear itself.
Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
Marek Vasut [Mon, 6 Mar 2023 14:53:44 +0000 (15:53 +0100)]
net: dwc_eth_qos: Drop unused dm_gpio_free() on STM32
The dm_gpio_free() is never called, because for stm32, the phy_reset_gpio
pointer is never valid. This is because only tegra186 ever claims the
phy_reset_gpio, all other platforms use the PHY framework to reset the
PHY instead. Drop the dm_gpio_free() and dm_gpio_is_valid().
Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Marek Vasut <marex@denx.de>
Marcel Ziswiler [Fri, 3 Mar 2023 13:26:37 +0000 (14:26 +0100)]
colibri-imx8x: update env memory layout
Update the distro config env memory layout for the Colibri iMX8X:
- kernel_comp_addr_r=0xb0000000 temporary area for uncompressing (ie FIT
images or Image.gz booted using booti)
- kernel_comp_size=0x08000000
- loadaddr=0x95400000 avoiding any reserved areas located before that
- fdt_addr_r = loadaddr + 128MB - allows for 128MB kernel
- scriptaddr = fdt_addr_r + 512KB - allows for 512KB fdt
- ramdisk_addr_r = scriptaddr + 512KB - allows for 512KB script
Idea of memory layout taken from commit bf1c94c46d71
("apalis-imx8: update env memory layout").
Note that for our regular BSP Layers and Reference Images for Yocto
Project an updated distro boot script is required (see
meta-toradex-bsp-common/recipes-bsp/u-boot/u-boot-distro-boot).
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@toradex.com>
Marek Vasut [Thu, 2 Mar 2023 22:40:44 +0000 (23:40 +0100)]
ARM: dts: imx: Add support for DH electronics i.MX8M Plus DHCOM on PDK3
Add support for DH electronics i.MX8M Plus DHCOM SoM on PDK3 carrier board.
Currently supported are serial console, EQoS and FEC ethernets, eMMC, SD,
SPI NOR and USB 3.0 host.
misc: imx: remove DM dependency for ocotp driver in SPL
The ocotp driver is available for regular and SPL builds using the
(SPL_)MXC_OCOTP configuration. Also, the ocotp driver does not support
the driver model (DM) configuration.
But, for SPL builds, the SPL_MXC_OCOTP configuration depends on
SPL_MISC which implies on SPL_DM.
This commit replaces the dependency on SPL_MISC with SPL_DRIVERS_MISC.
So the only requirement is to have enabled miscellaneous drivers for
the SPL.
Signed-off-by: Jean-Marie Lemetayer <j.lemetayer@kerlink.fr>
The i.MX8MP DHCOM SoM may come with either external RGMII PHY or
LAN8740Ai RMII PHY on the SoM attached to FEC MAC. Add pin mux
settings for both options, so that DT overlay can override these
settings on SoM variant with the LAN8740Ai PHY.
The i.MX8MP DHCOM SoM may come with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY on the SoM attached to EQoS MAC. Add pin
mux settings for both options, so that DT overlay can override
these settings on SoM variant with the LAN8740Ai PHY.
Marek Vasut [Sat, 11 Feb 2023 22:10:50 +0000 (23:10 +0100)]
arm64: imx8mp: Auto-detect PHY on i.MX8MP DHCOM
The i.MX8MP DHCOM SoM may be populated with either KSZ9131RNXI RGMII PHY
or LAN8740Ai RMII PHY attached to EQoS MAC, and either external RGMII PHY
or LAN8740Ai RMII PHY attached to FEC MAC. The SoM configuration can be
detected for each MAC by reading RX_CTL pull resistor state early on boot.
Make use of this, detect the exact PHY configuration, and patch control DT
accordingly so that the ethernet is configured correctly in U-Boot.
Marek Vasut [Sat, 11 Feb 2023 21:49:01 +0000 (22:49 +0100)]
ARM: imx: Add 2 GiB DRAM support for DH electronics i.MX8M Plus DHCOM
The DH electronics i.MX8M Plus DHCOM SoM currently supports only 4 GiB
of DRAM population option. Add another population option with 2 GiB of
DRAM. The chips used on the 2 GiB option are 2x K4F6E3S4HM-MGCJ .
configs: colibri-imx7: Fix bad block table in flash configuration
Make sure that the bad block table in flash is used on Colibri iMX7.
Without this configuration enabled U-Boot corrupts the bad block table
and Linux will update the table on each reboot. The corruption occurs
because if CONFIG_SYS_NAND_USE_FLASH_BBT is not set, U-boot will store
bad blocks out of band, while the Linux driver for the iMX7 will store
them in band in a bad block table.
Fixes: e0af4a568aa ("arm: dts: imx7: colibri: add raw NAND support") Signed-off-by: Stefan Eichenberger <stefan.eichenberger@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Pali Rohár [Wed, 29 Mar 2023 19:03:34 +0000 (21:03 +0200)]
arm: mvebu: Define all BOOTROM_ERR_MODE_* macros
A385 BootROM fills into bits [31:28] of register 0x182d0 tracing value,
which represents in which state BootROM currently is. BootROM fills one
of the possible values: 0x2 (CPU initialization), 0x3 (UART detection),
0x6 (UART booting), 0x8 (PCI Express booting), 0x9 (parallel or SPI NOR
booting), 0xA (parallel or SPI NAND booting), 0xB (SATA booting) and 0xE
(SD / eMMC booting).
Meaning of these values matches TRACE_* macros from Marvell soc_spec.h file:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/blob/u-boot-2013.01-armada-18.06/tools/marvell/doimage_mv/soc_spec.h
Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Wed, 29 Mar 2023 19:03:32 +0000 (21:03 +0200)]
arm: mvebu: Convert BOOT_FROM_* constants to function macros
This allows to merge BOOT_FROM_MMC and BOOT_FROM_MMC_ALT constants to one
macro. And also allows to extend other BOOT_FROM_* macros for other
variants.
Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
A385 BootROM treats strapping configuration 0x3f as invalid. When booting
fails (e.g. because of invalid configuration) then BootROM fallbacks to
UART booting.
Detecting BootROM fallback to UART booting is implemented in U-Boot since
commit 14df0dbeca3b ("ARM: mach-mvebu: handle fall-back to UART boot").
So there is no need to define BOOT_FROM_UART_ALT constant and special
handling for it anymore, remove it.
This change effectively revers commit 5321ace704d6 ("arm: mvebu: fix boot
from UART on ClearFog Base").
Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Tony Dinh <mibodhi@gmail.com> Tested-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
The Clearfog devices have only one SDHC device. This is either eMMC if
it is populated on the SOM or SDHC if not. The Linux device tree assumes
the SDHC case. Detect if the device is an eMMC and fixup the device-tree
so it will be detected by Linux.
Ported from vendor repo at https://github.com/SolidRun/u-boot
Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Martin Rowe [Sat, 25 Mar 2023 00:02:44 +0000 (10:02 +1000)]
arm: mvebu: clearfog: Add defconfig for SPI booting
This new clearfog_spi_defconfig file is a copy of existing
clearfog_defconfig file modified to instruct build system to generate
final kwbimage for SPI booting and to store the environment in SPI.
Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Martin Rowe [Sat, 25 Mar 2023 00:02:43 +0000 (10:02 +1000)]
arm: mvebu: clearfog: Fix MMC detection
A388 Clearfog MMC is either SD Card or eMMC with different behaviour for
both. Setting the device to non-removable in the u-boot.dtsi allows both
to correctly detect the device.
Signed-off-by: Martin Rowe <martin.p.rowe@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
Ye Li [Fri, 3 Feb 2023 10:24:36 +0000 (18:24 +0800)]
power: pmic: Add NXP PCA9451A PMIC support
PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but
has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver
and add new type for PCA9451A.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Marek Vasut <marex@denx.de>
Fabio Estevam [Wed, 15 Feb 2023 18:24:44 +0000 (15:24 -0300)]
pico-imx6: Pass the mmc alias to fix boot regression
Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
After the sync with Linux in commit c2092e38fd66 ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a boot regression in which the eMMC card cannot be found anymore.
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the eMMC (esdhc3) was
mapped to mmc0.
Fixes: c2092e38fd66 ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
Ye Li [Tue, 31 Jan 2023 08:42:34 +0000 (16:42 +0800)]
imx8ulp_evk: Clear data at fdt_addr_r before booting kernel
When using dual boot mode, the DDR won't be reset when APD power off
or reboot. It has possibility that obsolete fdt data existing on
fdt_addr_r address. Then even nothing in EFI partitions, the distro boot
still continue to parse fdt and get uboot crashed.
Clear the data at fdt_addr_r, so the fdt header check in above case
will not pass.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 31 Jan 2023 08:42:33 +0000 (16:42 +0800)]
imx8ulp_evk: disable overflow of port0 for LPAV
Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
With overflow set, we see some issue that A35 may not able to get enough
bandwidth and A35 will report hrtimer takes too much time, workqueue
lockup. With overflow cleared, the issues are gone.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:32 +0000 (16:42 +0800)]
imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun
To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:28 +0000 (16:42 +0800)]
misc: fuse: Lock 8ULP ECC-protected fuse when programming
The ECC fuse on 8ULP can't be written twice. If any user did it, the
ECC value would be wrong then cause accessing problem to the fuse.
The patch will lock the ECC fuse word to avoid this problem.
For iMX9, the OTP controller automatically prevents an ECC fuse word to
be written twice. So it does not need the setting.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:27 +0000 (16:42 +0800)]
misc: fuse: Update fuse mapping for 8ULP S400 API
Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Alice Guo <alice.guo@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:26 +0000 (16:42 +0800)]
imx: sentinel: Update S400 API get info message structure
From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
projects / uboot.git / log