Sandeep Tripathy [Mon, 17 Aug 2020 14:52:13 +0000 (20:22 +0530)]
psci: utility api to invoke stop for other cores
The API can be used to invoke a 'stop_func' callback for all
other cores from any initiating core. Optionally it can also
wait for other cores to power down. There may be various use
of such API by platform. Ex: Platform may use this to power
down all other cores from a crashed core.
Pramod Kumar [Wed, 5 Feb 2020 05:57:57 +0000 (11:27 +0530)]
lib: cpu: Check SCU presence in DSU before accessing DSU registers
The DSU contains system control registers in the SCU and L3 logic to
control the functionality of the cluster. If "DIRECT CONNECT" L3
memory system variant is used, there won't be any L3 cache,
snoop filter, and SCU logic present hence no system control register
will be present. Hence check SCU presence before accessing DSU register
for DSU_936184 errata.
arm_fpga: Add support to populate the CPU nodes in the DTB
At the moment BL31 dynamically discovers the CPU topology of an FPGA
system at runtime, but does not export it to the non-secure world.
Any BL33 user would typically looks at the devicetree to learn about
existing CPUs.
This patch exports a minimum /cpus node in a devicetree to satisfy
the binding. This means that no cpumaps or caches are described.
This could be added later if needed.
An existing /cpus node in the DT will make the code bail out with a
message.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I589a2b3412411a3660134bdcef3a65e8200e1d7e
Add support to export a /cpus node to the device tree.
This patch creates and populates the /cpus node in a device tree
based on the existing topology. It uses the minimum required nodes
and properties to satisfy the binding as specified in
https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/cpus.txt
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I03bf4e9a6427da0a3b8ed013f93d7bc43b5c4df0
spd: trusty: allow clients to retrieve service UUID
This patch implements support for the 64-bit and 32-bit versions of
0xBF00FF01 SMC function ID, as documented by the SMCCC, to allow
non-secure world clients to query SPD's UUID.
In order to service this FID, the Trusty SPD now increases the range
of SMCs that it services. To restrict Trusty from receiving the extra
SMC FIDs, this patch drops any unsupported FID.
Verified with TFTF tests for UID query and internal gtest for Trusty.
anzhou [Tue, 4 Aug 2020 14:05:19 +0000 (22:05 +0800)]
Tegra: common: fixup the bl31 code size to be copied at reset
If the CPU doesn't run from BL31_BASE, the firmware needs to be
copied from load address to BL31_BASE during cold boot. The size
should be the actual size of the code, which is indicated by the
__RELA_END__ linker variable.
This patch updates the copy routine to use this variable as a
result.
anzhou [Wed, 5 Aug 2020 14:34:13 +0000 (22:34 +0800)]
Tegra: common: disable GICC after domain off
The the GIC CPU interface should be disabled after cpu off. The
Tegra power management code should mark the connected core as asleep
as part of the CPU off sequence.
This patch disables the GICC after CPU off as a result.
anzhou [Fri, 26 Jun 2020 07:21:10 +0000 (15:21 +0800)]
Tegra: fixup CNTPS_TVAL_EL1 delay timer reads
The delay_timer driver for Tegra uses the CNTPS_TVAL_EL1 secure, physical,
decrementing timer as the source. The current logic incorrectly marks this
as an incrementing timer, by negating the timer value.
This patch fixes the anomaly and updates the driver to remove this logic.
Tegra: add platform specific 'runtime_setup' handler
Tegra SoCs would like the flexibility to perform chip specific actions
before we complete cold boot. This patch introduces a platform specific
'runtime_setup' handler to provide that flexibility.
The SVE CPU extension library reads the id_aa64pfr0_el1 register to
check if SVE is enabled. Tegra platforms disabled ENABLE_SVE_FOR_NS for
pre-8.2 platforms, but this flag can safely be enabled now that the
library can enable the feature at runtime.
This patch updates the makefile to remove "ENABLE_SVE_FOR_NS = 0"
as a result.
Jimmy Brisson [Tue, 4 Aug 2020 21:27:51 +0000 (16:27 -0500)]
Move static vars into functions in bl1
This reduces the scope of these variables and resolves Misra violations
such as:
bl1/aarch64/bl1_context_mgmt.c:21:[MISRA C-2012 Rule 8.9 (advisory)]
"bl1_cpu_context" should be defined at block scope.
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: I9b0b26395bce07e10e61d10158c67f9c22ecce44
In the case of Juno AArch32, platform security configuration
gets done from both BL2 and SP_MIN(BL32) components when
JUNO_AARCH32_EL3_RUNTIME and RESET_TO_SP_MIN build options
are set.
Fix is provided to avoid Platform security configuration from
SP_MIN when it is already done in BL2.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I702e91dacb4cdd2d10e339ddeaea91289bef3229
plat/arm: Get the base address of nv-counters from device tree
Using the Fconf, register base address of the various nv-counters
(currently, trusted, non-trusted nv-counters) are moved to the
device tree and retrieved during run-time. This feature is
enabled using the build option COT_DESC_IN_DTB.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I236f532e63cea63b179f60892cb406fc05cd5830
dtsi: Update the nv-counter node in the device tree
Created a header file defining the id of the various nv-counters
used in the system.
Also, updated the device tree to add 'id' property for the trusted
and non-trusted nv-counters.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ia41a557f7e56ad4ed536aee11c7a59e078ae07c0
Varun Wadekar [Mon, 26 Aug 2019 17:20:53 +0000 (10:20 -0700)]
Tegra: memctrl: platform setup handler functions
The driver initially contained the setup steps to help Tegra186
and Tegra194 SoCs. In order to support future SoCs and make sure
that the driver remains generic enough, some code should be moved
to SoC.
This patch creates a setup handler for a platform to implement its
initialization sequence.
The stream ID security configuration settings shall be done by the
previous level bootloader. This change removes the same settings
from the Tegra194 platform code as a result.
The stream ID override configuration is saved during System Suspend
as part MB1 bct. This change removes the same support from the Tegra194
platform code as a result.
Varun Wadekar [Wed, 11 Dec 2019 21:22:21 +0000 (13:22 -0800)]
Tegra: debug prints indicating SC7 entry sequence completion
This patch adds prints to display the completion of System Suspend
programming sequence for Tegra platforms. The console needs to
be kept alive until the very end of the System Suspend sequence as
a result.
Tegra194: memctrl: update TZDRAM base at 1MB granularity
The Memory controller expects the TZDRAM base value at 1MB granularity
and the current driver does not respect that limitation. This patch
fixes that anomaly.
David Pu [Fri, 7 Jun 2019 22:30:17 +0000 (15:30 -0700)]
Tegra194: ras: split up RAS error clear SMC call.
In order to make sure SMC call is within 25us, this patch reduces number of RAS
errors accessed to 8 at most for each SMC call and takes a input/output
parameter to specify in progress RAS error record index.
The measured SMC call latency is about 20us under Linux test kernel driver.
Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f Signed-off-by: David Pu <dpu@nvidia.com>
Varun Wadekar [Fri, 15 Nov 2019 23:46:14 +0000 (15:46 -0800)]
Tegra194: add memory barriers during DRAM to SysRAM copy
This patch adds memory barriers to the trampoline code copying TZDRAM
contents to SysRAM during exit from System Suspend. These barriers
make sure that all the copies go through before we start executing in
SysRAM.
Anthony Zhou [Wed, 4 Dec 2019 06:58:23 +0000 (14:58 +0800)]
Tegra: sip: add VPR resize enabled check
The Memory Controller provides a control register to check
if the video memory can be resized. The previous bootloader
might have locked this feature, which will be reflected by
this register.
This patch reads the control register before processing
a video memory resize request. An error code, -ENOTSUP,
is returned if the feature is locked.
Change-Id: Ia1d67f7a94aa15c6b18ff5c9b9b952e179596ae3 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Anthony Zhou [Wed, 13 Nov 2019 10:36:07 +0000 (18:36 +0800)]
Tegra194: add redundancy checks for MMIO writes
MMIO writes should verify that the writes actually went through.
Read the value back after the write operation, perform assert
if the read back value is not same as the write value.
Change-Id: Id2ceb014116f3aa6a9e86505ca1ae9911470a679 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
During boot the platform enables dual execution for Xavier CPUs.
This patch reads back the ACTLR_ELx register to verify that the bit
is actually set. It asserts if the bit is not set.
Tegra194: verify firewall settings before resource use
The firewall settings for the hardware resources are present in the
Security Configuration Registers. The firewall settings are programmed
by other software components and so must be verified for correctness
before touching the hardware resources they protect.
This patch reads the firewall settings during early boot and asserts
if the settings mismatch.
Coverity warns about the risk of unintended sign-exension in some of the
calculations in spmi_arb.c. While the actual numbers used are small
enough that this cannot happen in practice, it's still a good idea to
clean them up by explicitly making the constants used unsigned.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia169e0f7c6b01b8041e8029e8c8d30ee596ba30d
Add support for hexadecimal and pointer format specifiers to snprintf()
The current implementation of snprintf() does not support pointer and
hexadecimal format specifiers, which can be needed, for instance, for
DTB manipulations.
This patch adds that functionality by borrowing some code from the
printf() implementation.
Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I2076ea46693a73a04890982bf20e3c633c2767fb
Merge changes from topic "tegra194-spmd" into integration
* changes:
Tegra194: introduce support for `SPD=spmd`
Tegra: introduce backend support to compile libfdt
Tegra: disable signed comparison
plat: common: include "bl_common.h" from plat_spmd_manifest.c
Julius Werner [Wed, 5 Jun 2019 19:40:35 +0000 (12:40 -0700)]
qti: Add SPMI PMIC arbitrator driver
This patch adds a very rudimentary driver for the SPMI arbitrator used
to access the PMIC. It doesn't support all the controller's actual
arbitration features, so it should probably not be used concurrently
with a running kernel (and it's also not optimized for performance). But
it can be used to set a few registers during boot or on shutdown to
control reset handling, which is all we need it for.
Change-Id: I8631c34a2a89ac71aa1ec9b8266e818c922fe34a Signed-off-by: Julius Werner <jwerner@chromium.org>
Julius Werner [Tue, 25 Aug 2020 01:34:38 +0000 (18:34 -0700)]
qti/sc7180: Fix GIC-600 support setting
The patch adding platform support for sc7180 landed around roughly the
same time as the patch that changed GICV3_IMPL to GICV3_SUPPORT_GIC600.
Thus the sc7180 Makefile is still using the old variable name which now
no longer does anything, and it hangs on boot due to the lacking GIC-600
support. This patch fixes the issue.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id76ada1445c3c5ac9a5a3697b4e749088b89d796
plat: common: include "bl_common.h" from plat_spmd_manifest.c
This patch includes the bl_common.h from plat_spmd_manifest.c to
fix the following compilation errors
<snip>
plat/common/plat_spmd_manifest.c: In function 'plat_spm_core_manifest_load':
plat/common/plat_spmd_manifest.c:130:18: error: implicit declaration of function 'page_align' [-Werror=implicit-function-declaration]
130 | pm_base_align = page_align(pm_base, UP);
| ^~~~~~~~~~
plat/common/plat_spmd_manifest.c:130:38: error: 'UP' undeclared (first use in this function); did you mean 'UL'?
130 | pm_base_align = page_align(pm_base, UP);
| ^~
| UL
plat/common/plat_spmd_manifest.c:130:38: note: each undeclared identifier is reported only once for each function it appears in
plat/common/plat_spmd_manifest.c:146:38: error: 'DOWN' undeclared (first use in this function)
146 | pm_base_align = page_align(pm_base, DOWN);
| ^~~~
cc1: all warnings being treated as errors
<snip>
The SMMU configuration can get corrupted or updated by
external clients during boot without our knowledge.
This patch introduces a "verify" function for the SMMU
driver, to check that the boot configuration settings are
intact. Usually, this function should be called at the
end of the boot cycle.
This function only calls panic() on silicon platforms.
Change-Id: I2ab45a7f228781e71c73ba1f4ffc49353effe146 Signed-off-by: George Bauernschmidt <georgeb@nvidia.com>
Varun Wadekar [Thu, 22 Aug 2019 18:52:36 +0000 (11:52 -0700)]
Tegra: TZDRAM setup from soc specific early_boot handlers
TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in the
newer chips.
This patch moves the TZDRAM setup to early_boot handlers for SoCs to
handle this scenario.
Varun Wadekar [Fri, 4 Oct 2019 18:40:56 +0000 (11:40 -0700)]
Tegra: print GICC registers conditionally
The GICC interface exists only on the interrupt controllers following
the GICv2 specification.
This patch prints the GICC register contents from the platform's macro,
plat_crash_print_regs' only when TEGRA_GICC_BASE is defined. This
allows platforms using future versions of the GIC specification to
still use this macro.
SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer required when calling console_core_putc. However, flushing the
console still requires the flush bit.
This patch removes the flush bit from the mailbox messages in
console_core_putc to improve ACK latency.
Original change by: Mustafa Bilgen <mbilgen@nvidia.com>
tools: Get the tool's binary name from the main makefile
Currently, the tool's makefile override the tool's binary name
which is already been defined in the main makefile.
Hence fix is provided so that the tool's makefile get the tool's
binary name from the main makefile instead of overriding it.
Change-Id: I8af2bd391a96bba2dbcddef711338a94ebf5f038 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Mark Dykes [Wed, 19 Aug 2020 19:11:33 +0000 (19:11 +0000)]
Revert "libc/memset: Implement function in assembler"
This reverts commit e7d344de01ad11b856233634717aafe9312697e4.
This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge. The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done. This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch.
Olivier Deprez [Fri, 21 Aug 2020 14:18:57 +0000 (14:18 +0000)]
Merge changes from topic "spm-secondary-cores" into integration
* changes:
SPMC: embed secondary core ep info into to SPMC context
SPMC: manifest changes to support multicore boot
SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
SPMD: handle SPMC message to register secondary core entry point
SPMD: introduce SPMC to SPMD messages
SPMD: register the SPD PM hooks
SPMD: add generic SPD PM handlers
SPMD: enhance SPMC internal boot states
SPMD: entry point info get helper
Olivier Deprez [Mon, 23 Mar 2020 08:53:06 +0000 (09:53 +0100)]
SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
Define SPMD PM hooks for warm boot and off events. svc_on_finish handler
enters the SPMC at the entry point defined by the secondary EP register
service. The svc_off handler notifies the SPMC that a physical core is
being turned off through a notification message.
SPMD: handle SPMC message to register secondary core entry point
Upon booting, the SPMC running on the primary core shall register the
secondary core entry points to which a given secondary core being woken
up shall jump to into the SPMC . The current implementation assumes the
SPMC calls a registering service implemented in the SPMD for each core
identified by its MPIDR. This can typically happen in a simple loop
implemented in the early SPMC initialization routines by passing each
core identifier associated with an entry point address and context
information.
This service is implemented on top of a more generic SPMC<=>SPMD
interface using direct request/response message passing as defined by
the FF-A specification.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I1f70163b6b5cee0880bd2004e1fec41e3780ba35
projects / arm-tf.git / log