Yann Gautier [Wed, 26 Feb 2020 12:39:44 +0000 (13:39 +0100)]
stm32mp1: add a function to get non-secure DDR size
This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.
Fixed below 'tautological-constant-compare' error when building the source
code with latest clang compiler <clang version 11.0.0>.
plat/common/plat_psci_common.c:36:2:
error: converting the result of '<<' to a boolean always evaluates
to true [-Werror,-Wtautological-constant-compare]
PMF_STORE_ENABLE)
^
include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE'
PMF_STORE_ENABLE (1 << 0)
This error is observed beacuse of CASSERT placed in
"PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff:
CASSERT(_flags, select_proper_config);
where _flags = PMF_STORE_ENABLE (1 << 0) which always results true.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021
Varun Wadekar [Sun, 22 Mar 2020 22:58:02 +0000 (15:58 -0700)]
Tegra194: se: increase max. operation timeout to 1 second
This patch increases the maximum timeout value for SE operation
completion to 1 second. This takes care of some corner cases where
an operation might take more time than the previous timeout value
of 100ms.
Olivier Deprez [Thu, 19 Mar 2020 08:27:11 +0000 (09:27 +0100)]
spmd: skip loading of secure partitions on pre-v8.4 platforms
When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.
Yann Gautier [Wed, 18 Mar 2020 13:50:50 +0000 (14:50 +0100)]
io: io_stm32image: correct possible NULL pointer dereference
This issue was found with cppcheck in our downstream code:
[drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]:
(warning) Either the condition 'buffer!=0U' is redundant or there is
possible null pointer dereference: local_buffer.
Yann Gautier [Wed, 18 Mar 2020 13:35:27 +0000 (14:35 +0100)]
plat/st: correctly check pwr-regulators node
This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
(warning) Identical condition 'node<0', second condition is always false
The second test has to check variable pwr_regulators_node.
Yann Gautier [Wed, 11 Mar 2020 16:17:51 +0000 (17:17 +0100)]
plat/st: correct static analysis tool warning
Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
symbol 'fdt_get_node_parent_address_cells' was not declared.
Should it be static?
plat/st/common/stm32mp_dt.c:123:5: warning:
symbol 'fdt_get_node_parent_size_cells' was not declared.
Should it be static?
As those 2 functions are only used by assert(), put them under
ENABLE_ASSERTIONS flag.
Yann Gautier [Wed, 11 Mar 2020 16:16:49 +0000 (17:16 +0100)]
raw_nand: correct static analysis tool warning
Correct the following warning given by sparse tool:
include/drivers/raw_nand.h:158:3: warning:
symbol '__packed' was not declared. Should it be static?
Yann Gautier [Wed, 11 Mar 2020 16:09:21 +0000 (17:09 +0100)]
spi: stm32_qspi: correct static analysis issues
Sparse issue:
drivers/st/spi/stm32_qspi.c:445:5:
warning: symbol 'stm32_qspi_init' was not declared. Should it be static?
Cppcheck issue:
[drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]:
(style) Variable 'len' is reassigned a value before the old one has been
used.
[drivers/st/spi/stm32_qspi.c:178]:
(style) The scope of the variable 'timeout' can be reduced.
Manish Pandey [Mon, 23 Mar 2020 15:24:02 +0000 (15:24 +0000)]
Merge changes from topic "tegra-downstream-03192020" into integration
* changes:
Tegra194: move cluster and CPU counter to header file.
Tegra: gicv2: initialize target masks
spd: tlkd: support new TLK SMCs for RPMB service
Tegra210: trigger CPU0 hotplug power on using FC
Tegra: memctrl: cleanup streamid override registers
Tegra: memctrl_v2: remove support to secure TZSRAM
Tegra: include platform headers from individual makefiles
Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
Tegra194: SiP function ID to read SMMU_PER registers
Tegra: memctrl: map video memory as uncached
Tegra: remove support for USE_COHERENT_MEM
Tegra: remove circular dependency with common_def.h
Tegra: include missing stdbool.h
Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
Anthony Zhou [Mon, 11 Mar 2019 07:50:32 +0000 (15:50 +0800)]
Tegra194: move cluster and CPU counter to header file.
MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cannot be done.
This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER
macros to tegra_def.h as a result.
Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This patch adds support to handle following TLK SMCs:
{TLK_SET_BL_VERSION, TLK_LOCK_BL_INTERFACE, TLK_BL_RPMB_SERVICE}
These SMCs need to be supported in ATF in order to forward them to
TLK. Otherwise, these functionalities won't work.
Brief:
TLK_SET_BL_VERSION: This SMC is issued by the bootloader to supply its
version to TLK. TLK can use this to prevent rollback attacks.
TLK_LOCK_BL_INTERFACE: This SMC is issued by bootloader before handing off
execution to the OS. This allows preventing sensitive SMCs being used
by the OS.
TLK_BL_RPMB_SERVICE: bootloader issues this SMC to sign or verify RPMB
frames.
Tested by: Tests TLK can receive the new SMCs issued by bootloader
Change-Id: I57c2d189a5f7a77cea26c3f8921866f2a6f0f944 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>
sumitg [Fri, 8 Feb 2019 10:44:06 +0000 (16:14 +0530)]
Tegra210: trigger CPU0 hotplug power on using FC
Hotplug poweron is not working for boot CPU as it's being
triggerred using PMC and not with Flow Controller. This is
happening because "cpu_powergate_mask" is only getting set
for non-boot CPU's as the boot CPU's first bootup follows
different code path. The patch is marking a CPU as ON within
"cpu_powergate_mask" when turning its power domain on
during power on. This will ensure only first bootup on all
CPU's is using PMC and subsequent hotplug poweron will be
using Flow Controller.
Streamid override registers are passed to memctrl to program bypass
streamid for all the registers. There is no reason to bypass SMMU
for any of the client so need to remove register list and do not
set streamid_override_cfg.
Some Tegra186 platforms don't boot due to SDMMC failure so keep SDMMC
bypass as of now. Will revisit once these issues are fixed.
Ken Chang [Fri, 28 Dec 2018 00:44:12 +0000 (08:44 +0800)]
Tegra: memctrl: map video memory as uncached
Memmap video memory as uncached normal memory by adding flag
'MT_NON_CACHEABLE' in mmap_add_dynamic_region().
This improves the time taken for clearing the non-overlapping video
memory:
test conditions: 32MB memory size, EMC running at 1866MHz, t186
1) without MT_NON_CACHEABLE: 30ms ~ 40ms
<3>[ 133.852885] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 133.860471] _tegra_set_vpr_params[120]: begin
<3>[ 133.896481] _tegra_set_vpr_params[123]: end
<3>[ 133.908944] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 133.916397] _tegra_set_vpr_params[120]: begin
<3>[ 133.956369] _tegra_set_vpr_params[123]: end
<3>[ 133.970394] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 133.977934] _tegra_set_vpr_params[120]: begin
<3>[ 134.013874] _tegra_set_vpr_params[123]: end
<3>[ 134.025666] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 134.033512] _tegra_set_vpr_params[120]: begin
<3>[ 134.065996] _tegra_set_vpr_params[123]: end
<3>[ 134.075465] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 134.082923] _tegra_set_vpr_params[120]: begin
<3>[ 134.113119] _tegra_set_vpr_params[123]: end
<3>[ 134.123448] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 134.130790] _tegra_set_vpr_params[120]: begin
<3>[ 134.162523] _tegra_set_vpr_params[123]: end
<3>[ 134.172413] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 134.179772] _tegra_set_vpr_params[120]: begin
<3>[ 134.209142] _tegra_set_vpr_params[123]: end
2) with MT_NON_CACHEABLE: 10ms ~ 18ms
<3>[ 102.108702] vpr-heap: update vpr base to 0x00000000c6000000, size=e000000
<3>[ 102.116296] _tegra_set_vpr_params[120]: begin
<3>[ 102.134272] _tegra_set_vpr_params[123]: end
<3>[ 102.145839] vpr-heap: update vpr base to 0x00000000c6000000, size=c000000
<3>[ 102.153226] _tegra_set_vpr_params[120]: begin
<3>[ 102.164201] _tegra_set_vpr_params[123]: end
<3>[ 102.172275] vpr-heap: update vpr base to 0x00000000c6000000, size=a000000
<3>[ 102.179638] _tegra_set_vpr_params[120]: begin
<3>[ 102.190342] _tegra_set_vpr_params[123]: end
<3>[ 102.197524] vpr-heap: update vpr base to 0x00000000c6000000, size=8000000
<3>[ 102.205085] _tegra_set_vpr_params[120]: begin
<3>[ 102.216112] _tegra_set_vpr_params[123]: end
<3>[ 102.224080] vpr-heap: update vpr base to 0x00000000c6000000, size=6000000
<3>[ 102.231387] _tegra_set_vpr_params[120]: begin
<3>[ 102.241775] _tegra_set_vpr_params[123]: end
<3>[ 102.248825] vpr-heap: update vpr base to 0x00000000c6000000, size=4000000
<3>[ 102.256069] _tegra_set_vpr_params[120]: begin
<3>[ 102.266368] _tegra_set_vpr_params[123]: end
<3>[ 102.273400] vpr-heap: update vpr base to 0x00000000c6000000, size=2000000
<3>[ 102.280672] _tegra_set_vpr_params[120]: begin
<3>[ 102.290929] _tegra_set_vpr_params[123]: end
Change-Id: I5f604064ce7b8b73ea9ad5860156ae5e2c6cc42a Signed-off-by: Ken Chang <kenc@nvidia.com>
Manish Pandey [Thu, 19 Mar 2020 21:06:18 +0000 (21:06 +0000)]
fvp: use two instances of Cactus at S-EL1
To demonstrate communication between SP's two instances of Cactus at
S-EL1 has been used.
This patch replaces Ivy SP with cactus-secondary SP which aligns with
changes in tf-a-tests repository.
Olivier Deprez [Fri, 28 Feb 2020 11:12:08 +0000 (12:12 +0100)]
spmc: manifest changes to support two sample cactus secure partitions
When using the SPM Dispatcher, the SPMC sits as a BL32 component
(BL32_IMAGE_ID). The SPMC manifest is passed as the TOS fw config
component (TOS_FW_CONFIG_ID). It defines platform specific attributes
(memory range and physical CPU layout) as well as the attributes for
each secure partition (mostly load address). This manifest is passed
to the SPMC on boot up. An SP package contains the SP dtb in the SPCI
defined partition manifest format. As the SPMC manifest was enriched
it needs an increase of tos_fw-config max-size in fvp_fw_config dts.
Merge changes from topic "tegra-downstream-03122020" into integration
* changes:
Tegra: assembly version of the 'plat_core_pos_by_mpidr' handler
Tegra194: reset power state info for CPUs
tlkd: remove system off/reset handlers
Tegra186: system resume from TZSRAM memory
Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
Tegra210: SE: switch SE clock source to CLK_M
Tegra: increase platform assert logging level to VERBOSE
spd: trusty: disable error messages seen during boot
Tegra194: enable dual execution for EL2 and EL3
Tegra: aarch64: calculate core position from one place
Tegra194: Update t194_nvg.h to v6.7
Varun Wadekar [Fri, 16 Nov 2018 04:44:40 +0000 (20:44 -0800)]
Tegra194: reset power state info for CPUs
We set deepest power state when offlining a core but that may not be
requested by non-secure sw which controls idle states. It will re-init
this info from non-secure software when the core come online.
This patch resets the power state in the non-secure world context
to allow it to start with a clean slate.
Varun Wadekar [Fri, 9 Nov 2018 17:08:16 +0000 (09:08 -0800)]
Tegra186: system resume from TZSRAM memory
TZSRAM loses power during System suspend, so the entire contents
are copied to TZDRAM before Sysem Suspend entry. The warmboot code
verifies and restores the contents to TZSRAM during System Resume.
This patch removes the code that sets up CPU vector to point to
TZSRAM during System Resume as a result. The trampoline code can
also be completely removed as a result.
Varun Wadekar [Thu, 9 Aug 2018 22:11:23 +0000 (15:11 -0700)]
Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary
CPUs to a different entry point, than cold boot. The cold boot entry
point has the ability to differentiate between a cold boot and a warm
boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By
reusing the same entry point, we can lock the CPU reset vector during
cold boot.
Varun Wadekar [Tue, 16 Oct 2018 23:05:41 +0000 (16:05 -0700)]
Tegra: increase platform assert logging level to VERBOSE
This patch increases the assert logging level for all Tegra platforms
to VERBOSE, to print the actual assertion condition to the console,
improving debuggability.
Merge changes from topic "rpix-multi-console" into integration
* changes:
rpi: docs: Update maintainers file to new RPi directory scheme
rpi: console: Autodetect Mini-UART vs. PL011 configuration
rpi3: build: Include GPIO driver in all BL stages
rpi: Allow using PL011 UART for RPi3/RPi4
rpi3: console: Use same "clock-less" setup scheme as RPi4
rpi3: gpio: Simplify GPIO setup
FVP: In BL31/SP_MIN, map only the needed DRAM region statically
Rather than creating entry in plat_arm_mmap array to map the
entire DRAM region in BL31/SP_MIN, only map a smaller region holding
HW_CONFIG DTB. Consequently, an increase in number of sub-translation
tables(level-2 and level-3) i.e., MAX_XLAT_TABLES is necessary to map
the new region in memory.
In order to accommodate the increased code size in BL31 i.e.,
PROGBITS, the max size of BL31 image is increased by 0x1000(4K).
Andre Przywara [Wed, 11 Mar 2020 15:18:03 +0000 (15:18 +0000)]
rpi: console: Autodetect Mini-UART vs. PL011 configuration
The Raspberry Pi has two different UART devices pin-muxed to GPIO 14&15:
One ARM PL011 one and the 8250 compatible "Mini-UART".
A dtoverlay parameter in config.txt will tell the firmware to switch
between the two: it will setup the right clocks and will configure the
pinmuxes accordingly.
To autodetect the user's choice, we read the pinmux register and check
its setting: ALT5 (0x2) means the Mini-UART is used, ALT0 (0x4) points
to the PL011.
Based on that we select the UART driver to initialise.
This will allow console output in any case.
Change-Id: I620d3ce68de6c6576599f2a405636020e1fd1376 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Wed, 11 Mar 2020 16:33:53 +0000 (16:33 +0000)]
rpi3: build: Include GPIO driver in all BL stages
So far the Raspberry Pi 3 build needs the GPIO driver just for BL2.
Upcoming changes will require some GPIO code in BL1 and BL31 also, so
move those driver files into the common source section.
This does not affect BL31 code size at all, and bl1.bin just increases
by 144 bytes, but doesn't affect the padded binary size at all.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I7639746dc241c1e69099d85d2671c65fa0108555
Andre Przywara [Tue, 10 Mar 2020 12:34:56 +0000 (12:34 +0000)]
rpi: Allow using PL011 UART for RPi3/RPi4
The Broadcom 283x SoCs feature multiple UARTs: the mostly used
"Mini-UART", which is an 8250 compatible IP, and at least one PL011.
While the 8250 is usually used for serial console purposes, it suffers
from a design flaw, where its clock depends on the VPU clock, which can
change at runtime. This will reliably mess up the baud rate.
To avoid this problem, people might choose to use the PL011 UART for
the serial console, which is pin-mux'ed to the very same GPIO pins.
This can be done by adding "miniuart-bt" to the "dtoverlay=" line in
config.txt.
To prepare for this situation, use the newly gained freedom of sharing
one console_t pointer across different UART drivers, to introduce the
option of choosing the PL011 for the console.
This is for now hard-coded to choose the Mini-UART by default.
A follow-up patch will introduce automatic detection.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05
Andre Przywara [Tue, 10 Mar 2020 12:33:16 +0000 (12:33 +0000)]
rpi3: console: Use same "clock-less" setup scheme as RPi4
In the wake of the upcoming unification of the console setup code
between RPi3 and RPi4, extend the "clock-less" setup scheme to the
RPi3. This avoid programming any clocks or baud rate registers,
which makes the port more robust against GPU firmware changes.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ida83a963bb18a878997e9cbd55f8ceac6a2e1c1f
Igor Opaniuk [Mon, 16 Mar 2020 21:07:16 +0000 (23:07 +0200)]
plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE
Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A53 is enabled).
Enable DEBUG_CONSOLE_A53 if DEBUG_CONSOLE is enabled.
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I8ca411d5544658b9bcc39e5340ec042c51088b96
Igor Opaniuk [Mon, 16 Mar 2020 20:55:42 +0000 (22:55 +0200)]
plat: imx: imx8qm: provide debug uart num as build param
This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.
Usage:
$ make PLAT=imx8qm IMX_DEBUG_UART=1 bl31
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: Ib5f5dd81ba0c8ad2b2dc5647ec75629072f511c5
Igor Opaniuk [Mon, 16 Mar 2020 20:49:16 +0000 (22:49 +0200)]
plat: imx: imx8_iomux: fix shift-overflow errors
This fixes shift overflow errors, when compiled with CONSOLE_DEBUG
support:
plat/imx/common/include/imx8_iomux.h:11:35: error: result of β1 << 31β
requires 33 bits to represent, but βintβ only has 32 bits
[-Werror=shift-overflow=]
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I0488e22c30314ba27caabc5c767164baa1e8004c
Louis Mayencourt [Fri, 28 Feb 2020 16:57:30 +0000 (16:57 +0000)]
fconf: Clean Arm IO
Merge the previously introduced arm_fconf_io_storage into arm_io_storage. This
removes the duplicate io_policies and functions definition.
This patch:
- replace arm_io_storage.c with the content of arm_fconf_io_storage.c
- rename the USE_FCONF_BASED_IO option into ARM_IO_IN_DTB.
- use the ARM_IO_IN_DTB option to compile out io_policies moved in dtb.
- propagate DEFINES when parsing dts.
- use ARM_IO_IN_DTB to include or not uuid nodes in fw_config dtb.
- set the ARM_IO_IN_DTB to 0 by default for fvp. This ensure that the behavior
of fvp stays the same as it was before the introduction of fconf.
Change-Id: Ia774a96d1d3a2bccad29f7ce2e2b4c21b26c080e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Max Shvetsov [Thu, 12 Mar 2020 15:16:40 +0000 (15:16 +0000)]
SPMD: Add support for SPCI_ID_GET
This patch introduces the `SPCI_ID_GET` interface which will return the
ID of the calling SPCI component. Returns 0 for requests from the
non-secure world and the SPCI component ID as specified in the manifest
for secure world requests.
Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Mention COT build option in trusted-board-boot-build.rst
Since commit 3bff910dc16ad5ed97d470064b25481d3674732b ("Introduce COT
build option"), it is now possible to select a different Chain of Trust
than the TBBR-Client one.
Make a few adjustments in the documentation to reflect that. Also make
some minor improvements (fixing typos, better formatting, ...) along
the way.
The TBBR documentation has been written along with an early
implementation of the code. At that time, the range of supported
encryption and hash algorithms was failry limited. Since then, support
for other algorithms has been added in TF-A but the documentation has
not been updated.
Instead of listing them all, which would clutter this document while
still leaving it at risk of going stale in the future, remove specific
references to the original algorithms and point the reader at the
relevant comprehensive document for further details.
Chris Kay [Thu, 12 Mar 2020 13:50:26 +0000 (13:50 +0000)]
juno/sgm: Maximize space allocated to SCP_BL2
To accommodate the increasing size of the SCP_BL2 binary, the base
address of the memory region allocated to SCP_BL2 has been moved
downwards from its current (mostly) arbitrary address to the beginning
of the non-shared trusted SRAM.
Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434 Signed-off-by: Chris Kay <chris.kay@arm.com>
projects / arm-tf.git / log