Patrick Delaunay [Thu, 14 Apr 2022 09:19:03 +0000 (11:19 +0200)]
feat(st-uart): add initialization with the device tree
Add the pincontrol configuration and clock enable in UART driver
with information found in the device tree.
This patch avoids an issue on STM32MP13x platform because the UART
configuration is reset by the ROM code for UART serial boot
(STM32MP_UART_PROGRAMMER=1).
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I575fd0e1026b857059abcfd4a3166eb3a239e1fd
Patrick Delaunay [Tue, 15 Mar 2022 10:20:56 +0000 (11:20 +0100)]
feat(stm32mp1): configure the serial boot load address
For product with 128MB DDR size, the OP-TEE is located at the end
of the DDR and the FIP can't be loaded at the default location
because it overlap the OP-TEE final location. So the default value
for DWL_BUFFER_BASE is invalid.
To avoid this conflict the serial boot load address = DWL_BUFFER_BASE
can be modified with a configuration flags.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Ie27b87c10c57fea5d4c6200ce4f624e775b9a080
Patrick Delaunay [Mon, 28 Feb 2022 10:02:35 +0000 (11:02 +0100)]
fix(stm32mp1): update the FIP load address for serial boot
Update the FIP load address and size for serial boot to support
product with a DDR size = 128MB
1/ Move the FIP location at the end of the first 128MB
2/ Reduce the DWL_BUFFER_SIZE to 16MB, to be coherent with the value
indicated in USB enumeration
- for STM32MP13x: "@SSBL /0x03/1*16Me"
- for STM32MP15x: "@Partition3 /0x03/1*16Me"
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: Id93bf00c64832c17426bfd78e060861275677ecc
refactor(st-uart): compute the over sampling dynamically
The parameter over_sampling of stm32_uart_init_s is not required
as it can be computed dynamically from clock rate of the serial
device and the requested baudrate.
Oversampling by 8 is allowed only for higher speed
(up to clock_rate / 8) to reduce the maximum receiver tolerance
to clock deviation.
This patch update the driver, the serial init struct and the
only user, the stm32cubeprogrammer over uart support.
Change-Id: I422731089730a288defeb7fa49886db65d0902b2 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
feat(sgi): remove override for `ARM_BL31_IN_DRAM` build-option
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
within the common makefile would deter these platforms from having this
flexibility. Remove the default override configuration for
`ARM_BL31_IN_DRAM`.
feat(sgi): configure SRAM and BL31 size for sgi platform
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-chip SRAM. Additionally, revise BL31 image size to accommodate
larger BL31 images of multi-chip platforms.
Merge changes from topic "mediatek upstream" into integration
* changes:
refactor(mt8188): move platform_def.h to mt8188/include
feat(mt8188): add MCUSYS support
feat(mt8188): add armv8.2 support
feat(mt8188): add DFD control in SiP service
feat(mt8188): add EMI MPU basic drivers
feat(mt8188): add DCM driver
feat(mt8188): add reset and poweroff functions
feat(mediatek): add more flexibility of mtk_pm.c
feat(mediatek): add more options for build helper
feat(mt8188): add LPM driver support
feat(mt8188): apply ERRATA for CA-78
fix(mediatek): remove unused cold_boot.[c|h]
fix(mediatek): wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE
feat(mt8186): add EMI MPU support for SCP and DSP
Fengquan Chen [Wed, 17 Aug 2022 02:42:15 +0000 (10:42 +0800)]
feat(mt8188): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC
Fix the "#if defined(FOO)" usage introduced by commit 7c2fe62f1
("fix(bl31): allow use of EHF with S-EL2 SPMC") since the defines are
always passed as -DFOO=0 or as -DFOO=1. The "#if defined(FOO)" will now
always be true which is wrong.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I84fb144debc9899727a1fc021acdd59b4a6f0171
feat(versal-net): add support for platform management
Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149
CAAM provides serial output during initialization, but the serial init
occurs after CAAM. This leads to serial output produced by CAAM init
function to be omitted and not displayed.
Change the order of initialization and call CAAM init after Serial. This
has no impact as Serial does not require CAAM to be initialized upfront.
Fixes: 2502709f60de ("plat: imx8m: Add caam module init on imx8m") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I09c0a5474a1babfb0b53c4455891689ec08b5bdb
Michal Simek [Wed, 31 Aug 2022 14:45:14 +0000 (16:45 +0200)]
feat(versal-net): add support for Xilinx Versal NET platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
Serial output is missing the EOL marker, which makes the output garbled.
Add EOL to the output, which adds a newline and makes log output
consistent.
Fixes: 77850c96f23b ("feat(plat/imx8m): do not release JR0 to NS if HAB is using it") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Franck LENORMAND <franck.lenormand@nxp.com> Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I58b67f441016122bc9361d7224d310522917eff0
Merge changes from topic "RDN2_WARM_REBOOT_WITH_SGI" into integration
* changes:
feat(sgi): enable css implementation of warm reset
feat(scmi): send powerdown request to online secondary cpus
feat(plat/arm/css): add interrupt handler for reboot request
refactor(psci): move psci_do_pwrdown_sequence() out of private header
feat(plat/arm/css): add per-cpu power down support for warm reset
feat(scmi): set warm reboot entry point
fix(gicv3): update the affinity mask to 8 bit
ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.
feat(scmi): send powerdown request to online secondary cpus
To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
it is the responsibility of firmware to implement the system view of
the reset or reboot operation. For the platforms supported by CSS,
trigger the reset/reboot operation by sending an SGI to rest all CPUs
which are online. The CPUs respond to this interrupt by initiating its
powerdown sequence.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
feat(plat/arm/css): add interrupt handler for reboot request
Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
refactor(psci): move psci_do_pwrdown_sequence() out of private header
Move the psci_do_pwrdown_sequence() function declaration from PSCI
private header to common header. The psci_do_pwrdown_sequence is
required to support warm reset, where each CPU need to execute the
powerdown sequence.
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Pranav Madhu [Sat, 11 Dec 2021 16:53:25 +0000 (22:23 +0530)]
feat(scmi): set warm reboot entry point
Before issuing the system power down command, set the trusted mailbox
to 0. This will ensure that in the case of a warm/cold reset, the
primary CPU executes from the cold boot sequence, clearing any stale
jump address at this location.
The script 'sp_mk_generator.py' was reworked in [1]. There was a
reference the variable 'data' left. This variable 'data' used to refer
to the json data of a the sp layout file.
This patch fixed the reference with the proper variable according to the
rework [1].
ICC_SRE_EL2 has only 4 bits, while others are RES0. The library programs
all four of them already, so there is no need to read the previous
settings from the actual register.
This patch removes the explicit register read as a result.
Merge changes from topic "xilinx-misc-changes" into integration
* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): remove additional 0x in %p print
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main
Rajan Vaja [Wed, 31 Aug 2022 10:54:34 +0000 (12:54 +0200)]
fix(xilinx): update define for ZynqMP specific functions
Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9
Rajan Vaja [Wed, 31 Aug 2022 10:54:40 +0000 (12:54 +0200)]
fix(xilinx): remove unnecessary header include
Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0
Rajan Vaja [Wed, 31 Aug 2022 10:54:38 +0000 (12:54 +0200)]
fix(xilinx): include missing header
pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf
Michal Simek [Wed, 14 Sep 2022 07:29:50 +0000 (09:29 +0200)]
fix(zynqmp): remove additional 0x in %p print
%p is already printing value in hex that's why 0x prefix is not needed.
Origin message looks like this
"NOTICE: Can't read DT at 0x0x100000"
and after fixing
"NOTICE: Can't read DT at 0x100000"
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If83c485a61441f6105d8cbd797f04060dfce2817
Michal Simek [Tue, 13 Sep 2022 09:48:53 +0000 (11:48 +0200)]
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main
Fix some Misra-C violations. The similar fixes were done by commit eb0d2b17722c ("fix(zynqmp): resolve misra R15.6 warnings") and commit dd1fe7178b57 ("fix(zynqmp): resolve misra R14.4 warnings").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I3ffa92724a09871f7f99c9ac6c326994c165e9bd
Michal Simek [Thu, 4 Aug 2022 07:18:06 +0000 (09:18 +0200)]
fix(zynqmp): move debug bl31 based address back to OCM
The commit 389594dfa7e6 ("fix(zynqmp): move bl31 with DEBUG=1 back to OCM")
tried to move address to OCM but address was actually out of OCM and likely
it was typo. Correct default address should be 0xfffe5000. If TF-A size is
bigger please select location DDR which should be fine for DEBUG cases.
Reported-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I055f3a59cdca527f6029fcc2a19d76be35924d24
feat(versal): update macro name to generic and move to common place
Update TZ_VERSION macro name to generic macro name and move to
common header file so that it can be used for keystoneb.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> Acked-by: Tanmay Shah <tanmay.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic3819eea78b6c7b51ffaa13081026dd191b76125
Tanmay Shah [Fri, 26 Aug 2022 22:06:00 +0000 (15:06 -0700)]
feat(versal): add infrastructure to handle multiple interrupts
Only one hardcode interrupt handler is supported as of now.
This is IPI interrupt between APU and PMC processor.
This patch adds infrastructure to register multiple interrupt
handlers. This infrastructure was used and tested for two
interrupts and so, interrupt id and handler container size is
2 which is defined by MAX_INTR_EL3. Interrupt id is not used
as container index due to size constraints. User is expected to
adjust MAX_INTR_EL3 based on how many interrupts are handled in
TF-A
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Change-Id: Id49d94f6773fbb6874ccf89c0d12572efc7e678e
Tanmay Shah [Fri, 26 Aug 2022 22:13:48 +0000 (15:13 -0700)]
fix(versal): add SGI register call version check
PM_FEATURE_CHECK is supported only for platform
management API. PM_LOAD_PDI command is not intended
for platform management. This patch removes version
check of PM_LOAD_PDI and adds version check of command
that is used for SGI registartion.
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
Change-Id: I353163109b639acab73120f405a811770e8831a0
This patch changes the definition of image_info_t to follow the TF-A
coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html
Max Yu [Thu, 8 Sep 2022 23:21:21 +0000 (23:21 +0000)]
docs(porting-guide): correct typo of "bits" to "bytes"
The CACHE_WRITEBACK_GRANULE is documented to be in bits, but
specifying the value in bits broke a build. Further investigation
suggests that the value should in fact be in bytes. See
https://github.com/ARM-software/arm-trusted-firmware/blob/master/include/arch/aarch64/
smccc_helpers.h#L101
and
https://gcc.gnu.org/onlinedocs/gcc-12.2.0/gcc/Common-Type-Attributes.html
Change-Id: I9a2b2fbe18d5a58a8f9aeb2726a0623f3484c88e Signed-off-by: Max Yu <maxlyu@google.com>
Akram Ahmad [Tue, 6 Sep 2022 10:23:25 +0000 (11:23 +0100)]
fix(cpus): workaround for Cortex-A78C erratum 2376749
Cortex-A78C erratum 2376749 is a Cat B erratum that applies
to revisions r0p1 and r0p2 of the A78C and is currently open.
The workaround is to set CPUACTLR2_EL1[0] to 1 to force
PLDW/PFRM ST to behave like PLD/PRFM LD and not cause
invalidations to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I3b29f4b7f167bf499d5d11ffef91a94861bd1383
projects / arm-tf.git / log