johpow01 [Tue, 4 Jan 2022 22:15:18 +0000 (16:15 -0600)]
fix(errata): workaround for Cortex-A510 erratum 1922240
Cortex-A510 erratum 1922240 is a Cat B erratum that applies to revision
r0p0 and is fixed in r0p1.
Since no errata framework code existed for A510 prior to this patch, it
has been added as well. Also some general cleanup changes in the CPU lib
makefile.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8c427ef255cb4b38ed3e5c2c7444fcef957277e4
Bipin Ravi [Sun, 6 Feb 2022 09:11:44 +0000 (03:11 -0600)]
fix(errata): workaround for Cortex-A710 erratum 2136059
Cortex-A710 erratum 2136059 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause
the CPP instruction to invalidate the hardware prefetcher state
trained from any EL.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43a86a365418fb663cc1b6ab1d365b4beddae0bc
Bipin Ravi [Sun, 6 Feb 2022 08:32:54 +0000 (02:32 -0600)]
fix(errata): workaround for Cortex-A710 erratum 2267065
Cortex-A710 erratum 2267065 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of the CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR_EL1[22] to 1'b1. Setting
CPUACTLR_EL1[22] will cause the CFP instruction to invalidate
all branch predictor resources regardless of context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia9085aaf9b2b6a2b25d03ab36bd3774839fac9aa
Bipin Ravi [Sun, 6 Feb 2022 07:29:31 +0000 (01:29 -0600)]
fix(errata): workaround for Cortex-X2 erratum 2216384
Cortex-X2 erratum 2216384 is a Cat B erratum that applies to
revisions r0p0, r1p0 and r2p0 of CPU. It is fixed in r2p1.
The workaround is to set CPUACTLR5_EL1[17] to 1'b1 followed by
applying an instruction patching sequence.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3c216161678887c06a28c59644e784e0c7d37bab
Bipin Ravi [Thu, 20 Jan 2022 06:01:04 +0000 (00:01 -0600)]
fix(errata): workaround for Cortex-X2 errata 2017096
Cortex-X2 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0. The workaround is to set CPUECLTR_EL1[8]
to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I3b740aedc95c2394f6b8d1186014d2b2f640ae05
feat(st-clock): check HSE configuration in serial boot
In case of programmer mode, the bootrom manages to auto-detect
HSE clock configuration. In order to detect a bad device tree
setting in BL2, it will crash during programming if the configuration
is not aligned with the auto-detection.
Support "disabled" status for oscillator in device tree.
At boot time, the clock tree initialization performs the following
tasks:
- enabling of the oscillators present in the device tree and not
disabled,
- disabling of the HSI oscillator if the node is absent or disabled
(always activated by bootROM).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Change-Id: I176276022334f3d97ba0250b54062f0ae970e239
Nicolas Le Bayon [Wed, 13 Nov 2019 10:46:31 +0000 (11:46 +0100)]
refactor(st-clock): improve DT parsing for PLL nodes
Add a function to get PLL settings from DT:
"cfg" property is mandatory, an error is generated if not found.
"frac" is optional, default value is returned if not found.
"csg" is optional too, a boolean value indicates if it has been
found, and its value is updated.
Store each PLL node validity information, this avoids parsing DT
several times.
Change-Id: I039466fbe1e67d160f7112814e7bb63b661804d0 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Merge changes from topic "st_mapping_update" into integration
* changes:
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
feat(st): map 2MB for ROM code
fix(stm32mp1): restrict DEVICE2 mapping in BL2
feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections
Because the BL2 is not relocated, the usage of BL2_IN_XIP_MEM
can be used. It reduces the binary size by removing all relocation
sections. XIP will not be used when STM32MP_USE_STM32IMAGE is
defined. Introduce new definitions for SEPARATE_CODE_AND_RODATA.
Yann Gautier [Thu, 16 Jan 2020 17:50:51 +0000 (18:50 +0100)]
refactor(stm32mp1): reduce MMU memory regions and split XLAT by context
Simplify the BL2 MMU mapping and reduce the memory regions
number. Split the XLAT define between BL2 and BL32 as binaries
do not share the same tables anymore.
fix(imx8mp): change the BL31 physical load address
Change BL31 load address to 0x970000. This was done by Change-Id
I96d572fc. But then changed back to 0x960000 by Change-Id I8308c629.
However, 0x970000 is the correct value thus we change it back again.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Change-Id: Ia0db4877123b89072f723d18e2bcce25ef38f47d
Manish Pandey [Fri, 7 Jan 2022 16:24:54 +0000 (17:24 +0100)]
Merge changes from topic "st_ddr_updates" into integration
* changes:
refactor(st-ddr): move basic tests in a dedicated file
refactor(st-ddr): reorganize generic and specific elements
feat(stm32mp1): allow configuration of DDR AXI ports number
refactor(st-ddr): update parameter array initialization
feat(st-ddr): add read valid training support
refactor(stm32mp1): remove the support of calibration result
fix(st-ddr): correct DDR warnings
Yann Gautier [Wed, 5 Jan 2022 17:02:46 +0000 (18:02 +0100)]
fix(st): manage UART clock and reset only in BL2
As the UART is already initialized, no need to check for UART clock
or reset in next BL. An issue can appear if the next BL device tree
(e.g HW_CONFIG) doesn't use the same clocks or resets (like SCMI ones).
Manoj Kumar [Wed, 5 Jan 2022 14:33:52 +0000 (14:33 +0000)]
fix(errata): workaround for Rainier erratum 1868343
Rainier CPU is based on Neoverse N1 R4P0 version which exhibits
the erratum 1868343. This patch inherits the workaround from
neoverse_n1.S file into rainier.S file for erratum 1868343.
Manish Pandey [Wed, 5 Jan 2022 16:28:13 +0000 (17:28 +0100)]
Merge changes I19f713de,Ib5bda93d,Id5dafc04,Id20e65e2 into integration
* changes:
feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.3
feat(plat/rcar3): modify type for Internal function argument
feat(plat/rcar3): modify sequence for update value for WUPMSKCA57/53
fix(plat/rcar3): fix to bit operation for WUPMSKCA57/53
Nicolas Le Bayon [Tue, 18 May 2021 08:01:30 +0000 (10:01 +0200)]
refactor(st-ddr): reorganize generic and specific elements
stm32mp_ddrctl structure contains DDRCTRL registers definitions.
stm32mp_ddr_info contains general DDR information extracted from DT.
stm32mp_ddr_size moves to the generic side.
stm32mp1_ddr_priv contains platform private data.
stm32mp_ddr_dt_get_info() and stm32mp_ddr_dt_get_param() allow to
retrieve data from DT. They are located in new generic c/h files in
which stm32mp_ddr_param structure is declared. Platform makefile
is updated.
Adapt driver with this new classification.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I4187376c9fff1a30e7a94407d188391547107997
Patrick Delaunay [Fri, 30 Apr 2021 15:31:52 +0000 (17:31 +0200)]
refactor(stm32mp1): remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.
The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by CubeMX.
This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
the optional "st,phy-cal"
After this patch the built-in calibration is always executed.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: I3fc445520c259f7f05730aefc25e64b328bf7159
Refactor the GPIO code to use a small lookup table instead of redundant or
repetitive code.
Signed-off-by: Jona Stubbe <tf-a@jona-stubbe.de>
Change-Id: Icf60385095efc1f506e4215d497b60f90e16edfd Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
The issue was reported by Coverity [1]. The return of the functions
regulator_disable() and regulator_enable() was not checked.
If they fail, this means there is an issue either with PMIC or I2C.
The board should the stop booting with a panic().
On closed chips, it is not allowed to open debug. The BSEC debug
register can not be rewritten.
On open chips, the debug is already open, no need to rewrite this
register. This part of code is just removed.
An INFO message is displayed if debug is disabled.
The freeze of the watchdog during debug is also removed.
In case of debug, this must be managed by the software that enables
the debugger.
Wing Li [Thu, 23 Dec 2021 19:32:08 +0000 (11:32 -0800)]
fix(ufs): delete call to inv_dcache_range for utrd
The utrd struct is allocated on the stack by ufs_check_resp's caller.
Invalidating the utrd struct is unnecessary since it's only read from,
and can cause other values stored on the stack (e.g. link register) to
be inadvertently invalidated.
Change-Id: Icd455b52beb2677fafc083d68d0bfa0645b7194b Signed-off-by: Wing Li <wingers@google.com>
Andre Przywara [Mon, 27 Dec 2021 15:10:49 +0000 (15:10 +0000)]
docs(allwinner): update SoC list and build options
Our list of possible Allwinner build targets was missing the newly
introduced R329 support. Fix that by adding a table with maps the SoC
names to the build target names.
Also add some explanation about the recently introduced PSCI power
management providers.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Icf5e304562c3082552bf08d7b26904caf9074936
Andre Przywara [Mon, 1 Nov 2021 00:17:37 +0000 (00:17 +0000)]
feat(allwinner): allow to skip PMIC regulator setup
For somewhat historical reasons we are doing some initial PMIC regulator
setup in BL31, as U-Boot does not (yet) have a PMIC driver. This worked
fine so far, but there is at least one board (OrangePi 3) that gets upset,
because the Ethernet PHY needs some *coordinated* bringup of *two*
regulators.
To avoid custom hacks, let's introduce a build option to keep doing the
regulator setup in TF-A. Defining SUNXI_SETUP_REGULATORS to 0 will break
support for some devices on some boards in U-Boot (Ethernet and HDMI),
but will allow to bring up the OrangePi 3 in Linux correctly. We keep
the default at 1 to not change the behaviour for all other boards.
After U-Boot gained proper PMIC support at some point in the future, we
will probably change the default to 0, to get rid of the less optimal
PMIC code in TF-A.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ie8e2583d0396f6eeaae8ffe6b6190f27db63e2a7
Yann Gautier [Fri, 10 May 2019 14:01:34 +0000 (16:01 +0200)]
feat(st-sdmmc2): manage cards power cycle
To correctly initialize the MMC devices, a power cycle is required.
For this we need to:
- disable vmmc-supply regulator
- make the power cycle required for SDMMC2 peripheral
- enable regulators
Nicolas Le Bayon [Mon, 18 Nov 2019 12:13:36 +0000 (13:13 +0100)]
refactor(st-pmic): split initialize_pmic()
print_pmic_info_and_debug() prints the PMIC version ID and displays
regulator information if debug is enabled.
It is under DEBUG flag and called after initialize_pmic() in BL2.
Change-Id: Ib81a625740b7ec6abb49cfca05e44c69efaa4718 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Pascal Paillet [Tue, 15 Dec 2020 17:26:39 +0000 (18:26 +0100)]
feat(regulator): add a regulator framework
Add a regulator framework to:
- provide an interface to consumers and drivers,
- connect consumers with drivers,
- handle most of devicetree-parsing,
- handle always-on and boot-on regulators,
- handle min/max voltages,
Pascal Paillet [Tue, 15 Dec 2020 17:28:34 +0000 (18:28 +0100)]
feat(stpmic1): add new services
Add support for ICC, sink mode, bypass mode,
active discharge and list voltages.
Handle LDO3 sink source mode in a different way to avoid
setting voltage while in sink source mode.
Etienne Carriere [Fri, 10 Jan 2020 07:31:13 +0000 (08:31 +0100)]
feat(stpmic1): add USB OTG regulators
Add regulators boost, pwr_sw1 and pwr_sw2 regulators related to
USB OTG supply BOOST, SW_OTG and SWIN/SWOUT. These regulators are
needed since manipulated during the suspend/resume power sequence
as per FDT description for stm32mp15x-xxx boards from
STMicroelectronics.
Nicolas Le Bayon [Fri, 15 Nov 2019 14:56:06 +0000 (15:56 +0100)]
refactor(st-pmic): improve driver usage
Store status of dt_pmic_status() as local static variable,
this avoids parsing DT several times.
In the same way, store nodes in dt_pmic_i2c_config() and
in dt_get_pmic_node() as local static variables.
Change-Id: I4585e9dfdde2847a369bffcc6f2b39ecc2b74de1 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
SYSCFG can be initialized later, after console is up, to display the
warnings or messages it could issue.
PMIC should be initialized earlier, before SYSCFG init.
Yann Gautier [Fri, 19 Nov 2021 10:35:46 +0000 (11:35 +0100)]
fix(sve): disable ENABLE_SVE_FOR_NS for AARCH32
With patch [1], ENABLE_SVE_FOR_NS is always enable.
Disable it for AARCH32 platforms, as the feature is not supported.
The warning message is replaced with an error, and the second override
is removed.
[1] dc78e62d80e6 ("feat(sme): enable SME functionality")
This is mainly a clock interface with clk_ops callbacks.
Those callbacks are: enable, disable, get_rate, set_parent,
and is_enabled.
This framework is compiled for STM32MP1.
Change-Id: I5119a2aeaf103ceaae7a60d9e423caf0c148d794 Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Rex-BC Chen [Tue, 9 Nov 2021 05:12:03 +0000 (13:12 +0800)]
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8186 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
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