There are no references to AARCH32, AARCH64 and
__ASSEMBLY__ macros in the TF-A code hence
removed the deprecated information mentioning about
these macros in the document.
Change-Id: I472ab985ca2e4173bae23ff7b4465a9b60bc82eb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Saurabh Gorecha [Wed, 14 Oct 2020 18:41:15 +0000 (00:11 +0530)]
plat:qti Mandate SMC implementaion and bug fix
implementation of SMC call SMCCC_ARCH_SOC_ID
adding debugging logs in mem assign call.
Checking range of param in mem_assign call is from CB_MEM_RAM
or CB_MEM_RESERVED.
Merge changes from topic "stm32mp1_plat_updates" into integration
* changes:
docs: update STM32MP1 with versions details
stm32mp1: get peripheral base address from a define
stm32mp1: add finished good variant in board identifier
Yann Gautier [Tue, 13 Oct 2020 09:27:05 +0000 (11:27 +0200)]
docs: update STM32MP1 with versions details
After introducing the new STM32MP1 SoC versions in patch [1], the
document describing STM32MP1 platform is updated with the information
given in the patch commit message.
Nicolas Le Bayon [Mon, 23 Sep 2019 09:18:32 +0000 (11:18 +0200)]
stm32mp1: add asserts in get_cpu_package() and get_part_number()
Change-Id: I2b702698d6be93da5ac86da1cbc98b3838315a5a Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
Lionel Debieve [Fri, 17 May 2019 14:01:18 +0000 (16:01 +0200)]
stm32mp1: add support for new SoC profiles
Update to support new part numbers.
Add new STM32 MPUs Part = STM32MP151F, STM32MP153F, STM32MP157F,
STM32MP151D, STM32MP153D, STM32MP157D
The STM32MP1 series is available in 3 different lines which are pin-to-pin
compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz,
3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz
and CAN FD
- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
Each line comes with a security option (cryptography & secure boot)
& a Cortex-A frequency option :
- A Basic + Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Basic + Cortex-A7 @ 800 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
Remove useless variable in stm32mp_is_single_core().
stm32mp1: add finished good variant in board identifier
Update the board info with the new coding including the finished good
variant:
Board: MBxxxx Var<CPN>.<FG> Rev.<Rev>-<BOM>
The OTP 59 coding is:
bit [31:16] (hex) => MBxxxx
bit [15:12] (dec) => Variant CPN (1....15)
bit [11:8] (dec) => Revision board (index with A = 1, Z = 26)
bit [7:4] (dec) => Variant FG : finished good (NEW)
bit [3:0] (dec) => BOM (01, .... 255)
Change-Id: I4fbc0c84596419d1bc30d166311444ece1d9123f Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
Jimmy Brisson [Tue, 4 Aug 2020 21:18:52 +0000 (16:18 -0500)]
Increase type widths to satisfy width requirements
Usually, C has no problem up-converting types to larger bit sizes. MISRA
rule 10.7 requires that you not do this, or be very explicit about this.
This resolves the following required rule:
bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None>
The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U |
0x3c0U" (32 bits) is less that the right hand operand
"18446744073709547519ULL" (64 bits).
This also resolves MISRA defects such as:
bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)]
In the expression "3U << 20", shifting more than 7 bits, the number
of bits in the essential type of the left expression, "3U", is
not allowed.
Further, MISRA requires that all shifts don't overflow. The definition of
PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues.
This fixes the violation by changing the definition to 1UL << 12. Since
this uses 32bits, it should not create any issues for aarch32.
This patch also contains a fix for a build failure in the sun50i_a64
platform. Specifically, these misra fixes removed a single and
instruction,
from the cm_setup_context function caused a relocation in
psci_cpus_on_start to require a linker-generated stub. This increased the
size of the .text section and caused an alignment later on to go over a
page boundary and round up to the end of RAM before placing the .data
section. This sectionn is of non-zero size and therefore causes a link
error.
The fix included in this reorders the functions during link time
without changing their ording with respect to alignment.
Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Alexei Fedorov [Tue, 6 Oct 2020 14:54:12 +0000 (15:54 +0100)]
TF-A: Add HASH_ALG default value to defaults.mk
This patch adds default value of 'sha256' for HASH_ALG
build flag to 'make_helpers\defaults.mk', according to
'docs\getting_started\build-options.rst'.
This fixes Measured Boot driver error when TF-A uses
default HASH_ALG value and TPM_HASH_ALG is set to
sha384 or sha512.
In the function gicv2_set_spi_routing, the signed value proc_num is cast
to unsigned int before being compared to other unsigned values in two
assert calls. The value proc_num can be a negative value, and once the
negative value is cast to unsigned it becomes a very large number which
will trigger the assert. This patch changes the assert cast so that the
unsigned values are cast to signed instead, keeping the same functionality
but allowing proc_num to be negative.
This bug can be seen when running the SDEI RM_ANY routing mode test in
TFTF on the Juno platform.
This patch also makes the usage of the proc_num variable in other gicv2
functions more clear.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If1b98eebb00bd9b73862e5e995e5e68c168170a6
Jimmy Brisson [Wed, 5 Aug 2020 18:44:05 +0000 (13:44 -0500)]
Don't return error information from console_flush
And from crash_console_flush.
We ignore the error information return by console_flush in _every_
place where we call it, and casting the return type to void does not
work around the MISRA violation that this causes. Instead, we collect
the error information from the driver (to avoid changing that API), and
don't return it to the caller.
Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
In heavy parallel builds, it has sometimes been seen issues with the
tool not generated before it was needed. Change some rules order and
dependency to solve that.
stm32mp1: add macros to define PLAT_PARTITION_MAX_ENTRIES
There were fixed values when computing PLAT_PARTITION_MAX_ENTRIES.
Use STM32_BL33_PARTS_NUM and STM32_RUNTIME_PARTS_NUM. The first one is
for the number of copies of BL33. The second one depends on the use case
SP_min or OP-TEE. For OP-TEE, there are 3 partitions. For SP_min, as it
is in the same binary as BL2, it is set to 0. It will be set to 1 if
BL32 is in a separate binary.
Yann Gautier [Thu, 23 Jan 2020 17:41:20 +0000 (18:41 +0100)]
stm32mp1: use ASFLAGS for binary paths
To simplify the rule that creates the concatenated binary, use ASFLAGS
instead of adding all paths in the AS command line. This allows a better
management if a binary is not present.
Yann Gautier [Thu, 14 May 2020 14:54:12 +0000 (16:54 +0200)]
stm32mp1: use internal MAKE_LD macro to generate stm32 linker files
The previous proprietary version was not correctly handling dependencies.
Using MAKE_LD from make_helpers files now correctly handles that.
The generated linker script is the same as before.
Clear interrupt flag register after each sector read to avoid
issue when checking the register status.
Without clearing the interrupt, the status read doesn't wait
properly the ready bit.
Cortex A77 erratum 1925769 is a Cat B erratum, present in older
revisions of the Cortex A77 processor core. The workaround is to
set bit 8 in the ECTLR_EL1 register, there is a small performance cost
(<0.5%) for setting this bit.
Andre Przywara [Wed, 7 Oct 2020 10:09:42 +0000 (11:09 +0100)]
fdt: Fix coverity complaint about 32-bit multiplication
Coverity raised an eyebrow over our GICR frame size calculation:
========
CID 362942: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
Potentially overflowing expression "nr_cores * gicr_frame_size" with type
"unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic,
and then used in a context that expects an expression of type "uint64_t"
(64 bits, unsigned).
========
Even with a GICv4 (256KB frame size) we need 16384 cores to overflow
32-bit, so it's not a practical issue.
But it's also easy to fix, so let's just do that: cast gicr_frame_size
to an unsigned 64-bit integer, so that the multiplication is done in the
64-bit realm.
Change-Id: Iad10e19b9e58d5fbf9d13205fbcef0aac5ae48af Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Usama Arif [Mon, 5 Oct 2020 09:18:52 +0000 (10:18 +0100)]
plat/arm: common: add guard for arm_get_rotpk_info_regs
Only define arm_get_rotpk_info_regs if ROTPK is in registers,
i.e. (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID). This will
allow platform build without definition of TZ_PUB_KEY_HASH_BASE
if dedicated registers for ROTPK are not available on the platform.
Change-Id: I74ee2d5007f5d876a031a1efca20ebee2dede0c7 Signed-off-by: Usama Arif <usama.arif@arm.com>
Document the code review process in TF-A.
Specifically:
* Give an overview of code review and best practices.
* Give guidelines for the participants in code review.
* Outline responsibilities of each type of participant.
* Explain the Gerrit labels used in the review process.
Change-Id: I519ca4b2859601a7b897706e310f149a0c92e390 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: David Horstmann <david.horstmann@arm.com>
Yann Gautier [Mon, 5 Oct 2020 07:54:09 +0000 (09:54 +0200)]
bl32: use SORT_BY_ALIGNMENT macro in sp_min.ld.S
The macro SORT_BY_ALIGNMENT is used for .text* and .rodata*. This allows
reducing the space lost to object alignment. This is an alignment with
the following patch: ebd6efae67c6a086bc97d807a638bde324d936dc
Some comments are also aligned with other linker scripts.
plat: marvell: armada: a3k: rename the UART images archive
Add *.bin extension to UART recovery images archive name.
Such naming will cause the UART recovery images to be copied to the
Buildroot output folder upon flash image build.
Change-Id: I6992df1ab2ded725bed58e5baf245ae92c4cb289 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking the destination RAM address != 0.
This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform
allowing to bypass the above check in debug mode.
Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
marvell: comphy: cp110: add support for USB comphy polarity invert
The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.
Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
marvell: comphy: cp110: add support for SATA comphy polarity invert
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.
Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
drivers: marvell: mochi: Update AP incoming masters secure level
Do not force non-secure access level for PIDI masters when LLC_SRAM
is enabled. The EIP197 is located on CP0 and need to access secure
SRAM in AP LLC. This requires EIP197 DMA to have AXPROT[1]=0 and not
changed when forwarded to address decoding tables.
Change-Id: I8962db94a124350c14220ba6d0364d294ae4664a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
CNTVAL reflects the global system counter value in binary format.
Due to this erratum, the CNTVAL value presented to the processor
may be incorrect for several clock cycles.
Workaround: Override the default value of AP Register Device General
control 20 [19:16] and AP Register Device General Control 21 [11:8]
to the value of 0x3.
Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Cortex A76 erratum 1868343 is a Cat B erratum, present in older
revisions of the Cortex A76 processor core. The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.
This workaround is the same as workarounds for errata 1262606 and 1275112, so all 3 have been combined into one function call.
Andre Przywara [Fri, 2 Oct 2020 10:54:56 +0000 (11:54 +0100)]
spmd: Fix signedness comparison warning
With -Wsign-compare, compilers issue a warning in the SPMD code:
====================
services/std_svc/spmd/spmd_pm.c:35:22: error: comparison of integer
expressions of different signedness: 'int' and 'unsigned int'
[-Werror=sign-compare]
35 | if ((id < 0) || (id >= PLATFORM_CORE_COUNT)) {
| ^~
cc1: all warnings being treated as errors
====================
Since we just established that "id" is positive, we can safely cast it
to an unsigned type to make the comparison have matching types.
Change-Id: I6ef24804c88136d7e3f15de008e4fea854f10ffe Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Crypto library: Migrate support to MbedTLS v2.24.0
This patch migrates the mbedcrypto dependency for TF-A
to mbedTLS repo v2.24.0 which is the latest release tag.
The relevant documentation is updated to reflect the
use of new version.
Merge changes from topic "fpga_generic" into integration
* changes:
arm_fpga: Add platform documentation
arm_fpga: Add post-build linker script
arm_fpga: Add ROM trampoline
arm_fpga: Add devicetree file
arm_fpga: Remove SPE PMU DT node if SPE is not available
arm_fpga: Adjust GICR size in DT to match number of cores
fdt: Add function to adjust GICv3 redistributor size
drivers: arm: gicv3: Allow detecting number of cores
Andre Przywara [Wed, 16 Sep 2020 16:13:33 +0000 (17:13 +0100)]
arm_fpga: Add post-build linker script
For the Arm Ltd. FPGAs to run, we need to load several payloads into the
FPGA's memory:
- Some trampoline code at address 0x0, to jump to BL31's entry point.
- The actual BL31 binary at the beginning of DRAM.
- The (generic) DTB image to describe the hardware.
- The actual non-secure payloads (kernel, ramdisks, ...)
The latter is application specific, but the first three blobs are rather
generic.
Since the uploader tool supports ELF binaries, it seems helpful to
combine these three images into one .axf file, as this also simplifies
the command line.
Add a post-build linker script, that combines those three bits into one
ELF file, together with their specific load addresses.
Include a call to "ld" with this linker script in the platform Makefile,
so it will be build automatically. The result will be called "bl31.axf".
Change-Id: I4a90da16fa1e0e83b51d19e5b1daf61f5a0bbfca Signed-off-by: Andre Przywara <andre.przywara@arm.com>
projects / arm-tf.git / log