Bryan O'Donoghue [Tue, 12 Mar 2019 12:09:51 +0000 (12:09 +0000)]
bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed
A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.
The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.
msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1.
This change ensures we capture the x field, which we are interested in and
not the f field which we are not.
Bryan O'Donoghue [Mon, 11 Mar 2019 15:36:07 +0000 (15:36 +0000)]
bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR
Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].
This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0]
fields of the SPSR. For the purposes of initial setup of the SPSR the x and
c fields should be sufficient and importantly will capture the necessary
lower-order control bits that f:c alone do not.
This is important to do to ensure the SPSR is set to the mode the platform
intends prior to performing an eret.
Masahisa Kojima [Thu, 7 Mar 2019 02:23:42 +0000 (11:23 +0900)]
plat/arm: mhu: make mhu driver generic
MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima [Thu, 7 Mar 2019 01:41:54 +0000 (10:41 +0900)]
plat/synquacer: enable SCMI support
Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific protocol(0x80).
This vendor specific protocol is used to get the dram mapping information
from SCP.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Makefile: fix linking with pie and binutils > 2.27
Since binutils 1a9ccd70f9a7[1] TFA will not link when the PIE option is
used:
aarch64-linux-gnu-ld: build/fvp/debug/bl31/bl31.elf: Not enough room
for program headers, try linking with -N
aarch64-linux-gnu-ld: final link failed: Bad value
This issue was also encountered by u-boot[2] and linux powerpc kernel
[3]. The fix is to provide --no-dynamic-linker for the linker. This
tells the linker that PIE does not need loaded program program headers.
Paul Beesley [Wed, 6 Mar 2019 15:28:11 +0000 (15:28 +0000)]
tools: Remove TODO from fiptool
It is quite unlikely that this number will ever change and, if it
does need to change, we should have a good reason to do so. It
seems that this comment is now redundant.
Change-Id: I409c764080748e338e9bc5606bbdcc475213fb6e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
The SCTLR.DSSBS bit is zero by default thus disabling speculative loads.
However, we also explicitly set it to zero for BL2 and TSP images when
each image initialises its context. This is done to ensure that the
image environment is initialised in a safe state, regardless of the
reset value of the bit.
Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Tien Hock, Loh [Tue, 12 Mar 2019 06:36:19 +0000 (14:36 +0800)]
drivers: synopsys: Fix synopsys MMC driver
There are some issues with synopsys MMC driver:
- CMD8 should not expect data (for SD)
- ACMD51 should expect data (Send SCR for SD)
- dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is
now handled in the dw_prepare function
- after the CMD completes, when doing dw_read, we need to invalidate cache
and wait for the data transfer to complete
- Need to set FIFO threshold, otherwise DMA might never get the interrupt
to read or write
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Yann Gautier [Fri, 8 Mar 2019 14:44:59 +0000 (15:44 +0100)]
Remove some warnings when using checkpatch with --strict option
Some checks are ignored as they do not match TF-A coding rules:
PREFER_KERNEL_TYPES, USLEEP_RANGE
or MISRA:
COMPARISON_TO_NULL, UNNECESSARY_PARENTHESES
Yann Gautier [Fri, 8 Mar 2019 14:44:00 +0000 (15:44 +0100)]
Add the possibility to pass options for checkpatch
It can be handy for example to add --strict option which can detect more
coding issues, even if not mandated by TF-A coding rules.
To use it:
CHECKPATCH_OPTS="--strict" make checkpatch
Yann Gautier [Wed, 6 Mar 2019 09:58:13 +0000 (10:58 +0100)]
.checkpatch.conf: ignore BRACES warnings
MISRA C:2012 Rule 15.6 asks to have braces for the body of an if,
for, or while statement.
This conflicts with checkpatch, and the warning should then be ignored.
Yann Gautier [Mon, 11 Mar 2019 09:04:38 +0000 (10:04 +0100)]
fdts: stm32mp1: add bsec node
This node is added in a new file stm32mp157c-security.dtsi.
This node includes OTPs that should be shadowed and made readable
to non secure world.
Explicitly add status and secure-status, as these OTPs are accessible
by secure and non-secure world.
Andre Przywara [Sun, 17 Feb 2019 22:10:11 +0000 (22:10 +0000)]
allwinner: regulators: pick correct DT subnode
So far the DT node describing the AXP803 PMIC used in many Allwinner A64
boards had only one subnode, so our code just entering the first subnode
to find all regulators worked fine.
However recent DT updates in the Linux kernel add more subnodes *before*
that, so we need to make sure to explicitly enter the "regulators"
subnode to find the information we are after.
Improve some DT node parsing error handling on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Heiko Stuebner [Tue, 5 Mar 2019 23:29:13 +0000 (00:29 +0100)]
Fixup register handling in aarch32 reset_handler
The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.
Adapt to use r8 and adapt the comment about registers allowed
to clober.
I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.
Fixes: a6f340fe58b9 ("Introduce the new BL handover interface") Cc: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Luca Ceresoli [Thu, 28 Feb 2019 21:15:35 +0000 (22:15 +0100)]
zynqmp: pm: Add support for setting PMU configuration object
Allow EL2 (e.g. U-Boot) to load the configuration object at runtime
into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot
and U-Boot SPL with PMU FW without hard-coding the configuration
object.
Joel Hutton [Tue, 26 Feb 2019 16:23:54 +0000 (16:23 +0000)]
doc: Update links within imported wiki content
This patch covers two changes:
- Links that refer to GitHub are updated to point to the
relevant content on trustedfirmware.org
- Internal links between documents have been updated,
with the required .rst suffix being added or due
to a change in the relative locations of the files.
Change-Id: Ibf87da7d2ece726d1c94a9b33a2bbc3129de7779 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Joel Hutton [Mon, 25 Feb 2019 15:18:56 +0000 (15:18 +0000)]
doc: Migrate a subset of the GitHub wiki content
With the TF wiki being migrated from GitHub to trustedfirmware.org,
some documents will be moved into the docs/ directory within the
repository rather than remaining as external content. The
appropriate action has been decided on a per-document basis.
Change-Id: Id0f615f3418369256f30d2e34e354a115389d105 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Alexei Fedorov [Wed, 6 Mar 2019 11:15:51 +0000 (11:15 +0000)]
BL31: Enable pointer authentication support in warm boot path
In the current Pointer Authentication support added in
commit b86048c40cb7d9ccd7aeac1681945676a6dc36ff
PAuth gets enabled in BL31 cold boot entrypoint only,
(see bl31_entrypoint() in bl31\aarch64\bl31_entrypoint.S)
but not in bl31_warm_entrypoint().
This results in EnIA bit [31] in SCTLR_EL3 not being set
and pointer authentication disabled after CPU wake-up event.
Tien Hock, Loh [Thu, 7 Mar 2019 03:34:20 +0000 (11:34 +0800)]
drivers: mmc: Fix some issues with MMC stack
Some bugs in MMC stack needs to be fixed:
- scr cannot be local as this will cause cache issue when invalidating
after the read DMA transfer is completed
- ACMD41 needs to send voltage information in initialization, otherwise the
command is a query, thus will not initialize the controller
- when checking device state, retry until the retries counter goes to zero
before failing
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
David Pu [Mon, 25 Feb 2019 18:52:41 +0000 (10:52 -0800)]
xlat_tables_v2: print xlat tables without recursion
This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.
David Pu [Fri, 22 Feb 2019 10:36:20 +0000 (02:36 -0800)]
xlat_tables_v2: unmap region without recursion.
This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.
David Pu [Fri, 22 Feb 2019 10:31:40 +0000 (02:31 -0800)]
xlat_tables_v2: map region without recursion.
This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.
Marek Vasut [Sat, 2 Mar 2019 14:34:36 +0000 (15:34 +0100)]
rcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCB
Configure the GPIO5 09 pin as input on the ULCB board by default,
since the pin is routed on the expansion connector and not connected
to anything by default.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Varun Wadekar [Fri, 1 Mar 2019 18:18:35 +0000 (10:18 -0800)]
Tegra: dummy support for the io_storage backend
This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.
The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.
Doc: Fix internal links in interrupt framework design guide
Some of the sections numbers have been incorrect since the document
structure has changed. Using references to sections rather than
hard-coded section numbers fixes the issue while making it more
future-proof to updates.
While converting the interrupt framework design document from Markdown
to reStructuredText format, see commit 6f6257476754 ("Convert
documentation to reStructuredText"), the structure of the document was
changed and one of the titles got lost. Fix that.
Anson Huang [Fri, 1 Mar 2019 02:51:38 +0000 (10:51 +0800)]
imx: make sure GIC redistributor is awake before initialization
GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.
On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.
This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].
David Pu [Fri, 22 Feb 2019 10:23:57 +0000 (02:23 -0800)]
xlat_tables_v2: find VA/idx with helper functions.
This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by the
specified mmap region. it reduces code duplication and cyclomatic code
complexity in xlat_tables_map/unmap_region functions.
David Pu [Fri, 22 Feb 2019 10:15:57 +0000 (02:15 -0800)]
xlat_tables_v2: get unmap action type with helper function.
This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmapping the
specified region.
it reduces cyclomatic code complexity in xlat_tables_unmap_region function.
John Tsichritzis [Thu, 28 Feb 2019 11:14:03 +0000 (11:14 +0000)]
Remove Mbed TLS dependency from plat_bl_common.c
Due to the shared Mbed TLS heap optimisation introduced in 6d01a463,
common code files were depending on Mbed TLS specific headers. This
dependency is now removed by moving the default, unoptimised heap
implementation inside the Mbed TLS specific files.
Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
Louis Mayencourt [Wed, 27 Feb 2019 14:24:16 +0000 (14:24 +0000)]
Cortex-A73: Implement workaround for errata 852427
In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.
Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt [Mon, 11 Feb 2019 11:25:50 +0000 (11:25 +0000)]
MPAM: enable MPAM EL2 traps
Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2
traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an
MPAM-unaware-hypervisor to be restricted by an MPAM-aware-guest.
Change-Id: I47bf3f833fa22baa590f83d49cc0e3f2974e698d Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
projects / arm-tf.git / log