Varun Wadekar [Tue, 14 Mar 2017 21:24:35 +0000 (14:24 -0700)]
Tegra186: mce: driver for the CPU complex power manager block
The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
offload engine for BPMP to do voltage related sequencing and for
hardware requests to be handled in a better latency than BPMP-firmware.
There are two interfaces to the MCEs - Abstract Request Interface (ARI)
and the traditional NVGINDEX/NVGDATA interface.
MCE supports various commands which can be used by CPUs - ARM as well
as Denver, for power management and reset functionality. Since the
linux kernel is the master for all these scenarios, each MCE command
can be issued by a corresponding SMC. These SMCs have been moved to
SiP SMC space as they are specific to the Tegra186 SoC.
Varun Wadekar [Tue, 25 Aug 2015 11:33:14 +0000 (17:03 +0530)]
Tegra186: platform support for Tegra "T186" SoC
Tegra186 is the newest SoC in the Tegra family which consists
of two CPU clusters - Denver and A57. The Denver cluster hosts
two next gen Denver15 CPUs while the A57 cluster hosts four ARM
Cortex-A57 CPUs. Unlike previous Tegra generations, all the six
cores on this SoC would be available to the system at the same
time and individual clusters can be powered down to conserve
power.
Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds driver for the Memory Controller (v2) in the newer
Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of
the proprietary block in the past.
Andre Przywara [Thu, 6 Oct 2016 15:54:53 +0000 (16:54 +0100)]
Add workaround for ARM Cortex-A53 erratum 855873
ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and invalidate" instructions.
For core revisions of r0p3 and later this can be done by setting a bit
in the CPUACTLR_EL1 register, so that hardware takes care of the promotion.
As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3,
we set the bit in firmware.
Also we dump this register upon crashing to provide more debug
information.
Enable the workaround for the Juno boards.
Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Modify ARM common makefile to use version 2 of the translation tables
library and include the new header in C files.
Simplify header dependencies related to this library to simplify the
change.
The following table contains information about the size increase in
bytes for BL1 after applying this patch. The code has been compiled for
different configurations of FVP in AArch64 mode with compiler GCC 4.9.3 20150413. The sizes have been calculated with the output of `nm` by
adding the size of all regions and comparing the total size before and
after the change. They are sumarized in the table below:
text bss data total
Release +660 -20 +88 +728
Debug +740 -20 +242 +962
Debug (LOG_LEVEL=50) +1120 -20 +317 +1417
Change-Id: I539e307f158ab71e3a8b771640001fc1bf431b29 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI twice each time.
Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.
This errata has been enabled for Juno.
The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.
Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Added APIs to add and remove regions to the translation tables
dynamically while the MMU is enabled. Only static regions are allowed
to overlap other static ones (for backwards compatibility).
A new private attribute (MT_DYNAMIC / MT_STATIC) has been added to
flag each region as such.
The dynamic mapping functionality can be enabled or disabled when
compiling by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1
or 0. This can be done per-image.
TLB maintenance code during dynamic table mapping and unmapping has
also been added.
Fixes ARM-software/tf-issues#310
Change-Id: I19e8992005c4292297a382824394490c5387aa3b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
- Whenever multiple invalid descriptors are found, only the first one
is printed, and a line is added to inform about how many descriptors
have been omitted.
- At the beginning of each line there is an indication of the table
level the entry belongs to. Example of the new output:
`[LV3] VA:0x1000 PA:0x1000 size:0x1000 MEM-RO-S-EXEC`
Change-Id: Ib6f1cd8dbd449452f09258f4108241eb11f8d445 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
The files affected by this patch don't really depend on `xlat_tables.h`.
By changing the included file it becomes easier to switch between the
two versions of the translation tables library.
Change-Id: Idae9171c490e0865cb55883b19eaf942457c4ccc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
The folder lib/xlat_tables_v2 has been created to store a new version
of the translation tables library for further modifications in patches
to follow. At the moment it only contains a basic implementation that
supports static regions.
This library allows different translation tables to be modified by
using different 'contexts'. For now, the implementation defaults to
the translation tables used by the current image, but it is possible
to modify other tables than the ones in use.
Added a new API to print debug information for the current state of
the translation tables, rather than printing the information while
the tables are being created. This allows subsequent debug printing
of the xlat tables after they have been changed, which will be useful
when dynamic regions are implemented in a patch to follow.
The common definitions stored in `xlat_tables.h` header have been moved
to a new file common to both versions, `xlat_tables_defs.h`.
All headers related to the translation tables library have been moved to
a the subfolder `xlat_tables`.
Change-Id: Ia55962c33e0b781831d43a548e505206dffc5ea9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Varun Wadekar [Fri, 17 Feb 2017 02:14:37 +0000 (18:14 -0800)]
spd: trusty: save context starting from the stack end
This patch uses the stack end to start saving the CPU context
during world switch. The previous logic, used the stack start
to save the context, thus overwriting the other members of the
context.
If Trusty is not running on the device, then Verified Boot is
not supported and the NS layer will fail gracefully later during
boot. This patch just returns success for the case when Trusty is
not running on the device and the bootloader issues SET_ROT_PARAMS
call during boot, so that we can at least boot non-Android images.
Varun Wadekar [Wed, 8 Jun 2016 04:21:59 +0000 (21:21 -0700)]
tlkd: execute standard SMC calls on the boot CPU
This patch checks if standard SMC calls, meant for TLK, are issued
only on the boot CPU. TLK is UP Trusted OS stack and so we need this
check to avoid the NS world calling into TLK from any other CPU.
The previous check tied TLK to CPU0, but the boot CPU can be other
than CPU0 in some scenarios.
Anthony Zhou [Wed, 20 Apr 2016 02:16:48 +0000 (10:16 +0800)]
spd: trusty: only process one function ID at a time
In multi-guest trusty environment, all guest's SMCs will be
forwarded to Trusty. This change only allows 1 guest's SMC
to be forwarded at a time and returns 'busy' status to all
other requests.
Change-Id: I2144467d11e3680e28ec816adeec2766bca114d4 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Anthony Zhou [Fri, 30 Oct 2015 22:03:41 +0000 (06:03 +0800)]
spd: trusty: pass VMID via X7
According to the ARM DEN0028A spec, hypervisor ID(VMID) should be stored
in x7 (or w7). This patch gets this value from the context and passes it
to Trusty. In order to do so, introduce new macros to pass five to eight
parameters to the Trusted OS.
Change-Id: I101cf45d0712e1e880466b2274f9a48af755c9fa Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Tue, 28 Feb 2017 16:23:59 +0000 (08:23 -0800)]
Tegra: enable SEPARATE_CODE_AND_RODATA build flag
This patch enables the SEPARATE_CODE_AND_RODATA build flag for all
Tegra platforms, to allow setting proper MMU attributes for the RO
data and the code.
Harvey Hsieh [Wed, 28 Dec 2016 13:53:18 +0000 (21:53 +0800)]
Tegra210: assert if afflvl0/1 have incorrect state-ids
The linux kernel v3.10 does not use System Suspend function ID, whereas
v4.4 uses it. This means affinity levels 0/1 will have different state id
values during System Suspend entry. This patch updates the assert criteria
to check both the state id values.
Damon Duan [Mon, 7 Nov 2016 11:37:50 +0000 (19:37 +0800)]
Tegra: init the console only if the platform supports it
Some platforms might want to keep the uart console disabled
during boot. This patch checks if the platform supports a
console, before calling console_init().
Tegra210: set core power state during cluster power down
This patch sets the core power state during cluster power down,
so that the 'get_target_pwr_state' handler can calculate the
proper states for all the affinity levels.
This patch adds support to identify the underlying platform
on which we are running. The currently supported platforms
are actual silicon and simulation platforms.
Soby Mathew [Tue, 14 Feb 2017 10:21:55 +0000 (10:21 +0000)]
AArch32: Enable override of plat_set_my_stack/plat_get_my_stack
This patch makes the default MP definitions of plat_get_my_stack()
and plat_set_my_stack() as weak so that they can be overridden by
the AArch32 Secure Payload if it requires.
Soby Mathew [Tue, 28 Feb 2017 22:58:29 +0000 (22:58 +0000)]
AArch32: Fix conditional inclusion of bakery_locks
Due to incorrect conditional compilation checks, bakery locks were
excluded from the CCN driver and the power controller driver for FVP
when BL32 was built as the EL3 Runtime Software in AArch32 mode.
This patch corrects the same.
PSCI: Optimize call paths if all participants are cache-coherent
The current PSCI implementation can apply certain optimizations upon the
assumption that all PSCI participants are cache-coherent.
- Skip performing cache maintenance during power-up.
- Skip performing cache maintenance during power-down:
At present, on the power-down path, CPU driver disables caches and
MMU, and performs cache maintenance in preparation for powering down
the CPU. This means that PSCI must perform additional cache
maintenance on the extant stack for correct functioning.
If all participating CPUs are cache-coherent, CPU driver would
neither disable MMU nor perform cache maintenance. The CPU being
powered down, therefore, remain cache-coherent throughout all PSCI
call paths. This in turn means that PSCI cache maintenance
operations are not required during power down.
- Choose spin locks instead of bakery locks:
The current PSCI implementation must synchronize both cache-coherent
and non-cache-coherent participants. Mutual exclusion primitives are
not guaranteed to function on non-coherent memory. For this reason,
the current PSCI implementation had to resort to bakery locks.
If all participants are cache-coherent, the implementation can
enable MMU and data caches early, and substitute bakery locks for
spin locks. Spin locks make use of architectural mutual exclusion
primitives, and are lighter and faster.
The optimizations are applied when HW_ASSISTED_COHERENCY build option is
enabled, as it's expected that all PSCI participants are cache-coherent
in those systems.
The PSCI implementation performs cache maintenance operations on its
data structures to ensure their visibility to both cache-coherent and
non-cache-coherent participants. These cache maintenance operations
can be skipped if all PSCI participants are cache-coherent. When
HW_ASSISTED_COHERENCY build option is enabled, we assume PSCI
participants are cache-coherent.
For usage abstraction, this patch introduces wrappers for PSCI cache
maintenance and barrier operations used for state coordination: they are
effectively NOPs when HW_ASSISTED_COHERENCY is enabled, but are
applied otherwise.
Also refactor local state usage and associated cache operations to make
it clearer.
Disallow using coherent memory with hardware-assisted coherency
ARM Trusted Firmware keeps certain data structures in a memory region
with non-cacheable attributes (termed as "coherent memory") to keep data
coherent with observers that are cache-coherent, and those not. These
data structures pertain to power management and mutual exclusion. Using
coherent memory also costs at least an additional page to map memory
with special memory attributes.
On systems with hardware-assisted coherency, all CPUs that participate
in power management and mutual exclusion are cache-coherent, obviating
the need for special memory attributes for such data structures.
Instead, they can be placed in normal memory, along with rest of data.
On systems with hardware-assisted coherency, where build option
HW_ASSISTED_COHERENCY will be set, also having USE_COHERENT_MEMORY
enabled only wastes a page of memory without any
benefit. Therefore, with HW_ASSISTED_COHERENCY set to 1, require that
USE_COHERENT_MEMORY is explicitly set to 0.
Enable data caches early with hardware-assisted coherency
At present, warm-booted CPUs keep their caches disabled when enabling
MMU, and remains so until they enter coherency later.
On systems with hardware-assisted coherency, for which
HW_ASSISTED_COHERENCY build flag would be enabled, warm-booted CPUs can
have both caches and MMU enabled at once.
build: Define build option for hardware-assisted coherency
The boolean build option HW_ASSISTED_COHERENCY is introduced to enable
various optimizations in ARM Trusted Software, when built for such
systems. It's set to 0 by default.
Soby Mathew [Tue, 14 Feb 2017 10:11:52 +0000 (10:11 +0000)]
Flush the GIC driver data after init
The GIC driver data is initialized by the primary CPU with caches
enabled. When the secondary CPU boots up, it initializes the
GICC/GICR interface with the caches disabled and there is a chance that
the driver data is not yet written back to the memory. This patch fixes
this problem by flushing the driver data after they have been
initialized.
Varun Wadekar [Tue, 7 Jun 2016 19:00:06 +0000 (12:00 -0700)]
Tegra: per-soc `get_target_pwr_state` handler
This patch implements a per-soc handler to calculate the target
power state for the cluster/system. A weak implementation of the
handler is provided for platforms to use by default.
For SoCs with multiple CPU clusters, this handler would provide
the individual cluster/system state, allowing the PSCI service to
flush caches during cluster/system power down.
Varun Wadekar [Mon, 23 May 2016 22:56:14 +0000 (15:56 -0700)]
Tegra: relocate BL32 image to TZDRAM memory
This patch adds support to relocate the BL32 image from the NS
memory to TZDRAM during cold boot. The NS memory buffer is
cleared out after the process completes.
Varun Wadekar [Sun, 5 Jun 2016 05:08:50 +0000 (22:08 -0700)]
Tegra: configure TZDRAM fence during early setup
This patch configures the TZDRAM fence during early platform
setup to allow the memory controller to enable DRAM encryption
before the TZDRAM actually gets used.
Varun Wadekar [Fri, 20 May 2016 23:21:22 +0000 (16:21 -0700)]
Tegra: GIC: differentiate between FIQs targeted towards EL3/S-EL1
This patch modifies the secure IRQ registration process to allow platforms
to specify the target CPUs as well as the owner of the IRQ. IRQs "owned"
by the EL3 would return INTR_TYPE_EL3 whereas those owned by the Trusted
OS would return INTR_TYPE_S_EL1 as a result.
Varun Wadekar [Tue, 29 Dec 2015 00:36:42 +0000 (16:36 -0800)]
Tegra: implement FIQ interrupt handler
This patch adds a handler for FIQ interrupts triggered when
the CPU is in the NS world. The handler stores the NS world's
context along with ELR_EL3/SPSR_EL3.
The NS world driver issues an SMC initially to register it's
handler. The monitor firmware stores this handler address and
jumps to it when the FIQ interrupt fires. Upon entry into the
NS world the driver then issues another SMC to get the CPU
context when the FIQ fired. This allows the NS world driver to
determine the CPU state and call stack when the interrupt
fired. Generally, systems register watchdog interrupts as FIQs
which are then used to get the CPU state during hangs/crashes.
Varun Wadekar [Mon, 28 Dec 2015 22:55:41 +0000 (14:55 -0800)]
Tegra: GIC: enable FIQ interrupt handling
Tegra chips support multiple FIQ interrupt sources. These interrupts
are enabled in the GICD/GICC interfaces by the tegra_gic driver. A
new FIQ handler would be added in a subsequent change which can be
registered by the platform code.
This patch adds the GIC programming as part of the tegra_gic_setup()
which now takes an array of all the FIQ interrupts to be enabled for
the platform. The Tegra132 and Tegra210 platforms right now do not
register for any FIQ interrupts themselves, but will definitely use
this support in the future.
Varun Wadekar [Thu, 5 May 2016 21:13:30 +0000 (14:13 -0700)]
Tegra: implement common handler `plat_get_target_pwr_state()`
This patch adds a platform handler to calculate the proper target power
level at the specified affinity level.
Tegra platforms assign a local state value in order of decreasing depth
of the power state i.e. for two power states X & Y, if X < Y then X
represents a shallower power state than Y. As a result, the coordinated
target local power state for a power domain will be the maximum of the
requested local power state values.
Wayne Lin [Thu, 31 Mar 2016 20:49:09 +0000 (13:49 -0700)]
Tegra: allow SiP smc calls from Secure World
This patch removes the restriction of allowing SiP calls only from the
non-secure world. The secure world can issue SiP calls as a result of
this patch now.
Change-Id: Idd64e893ae8e114bba0196872d3ec544cac150bf Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Thu, 24 Mar 2016 22:34:24 +0000 (15:34 -0700)]
Tegra: relocate code to BL31_BASE during cold boot
This patch adds support to relocate BL3-1 code to BL31_BASE in case
we cold boot to a different address. This is particularly useful to
maintain compatibility with legacy BL2 code.
This patch also checks to see if the image base address matches either
the TZDRAM or TZSRAM base.
dp-arm [Tue, 14 Feb 2017 15:22:13 +0000 (15:22 +0000)]
fiptool: Embed a pointer to an image within the image descriptor
Currently, fiptool uses two linked lists. One to chain together all
the images and one for all the image descriptors. Initially this was
done because not all images had a corresponding image descriptor.
This was the case for unknown images which existed in the FIP but
there was no descriptor in the builtin table for them. When support
for the --blob option came in, we started building descriptors for the
unknown images on the fly. As a result every image now has a
corresponding image descriptor and therefore it is no longer necessary
to keep track of them separately.
To simplify the design, maintain only a single linked list of image
descriptors. An image descriptor contains a pointer to the
corresponding image. If the pointer is NULL, then the descriptor is
skipped in all the operations. This approach simplifies the traversal
code and avoids redundant lookups.
The linked list of image descriptors is populated based on the
`toc_entries` array. This means that the order of the images in the
FIP file remains the same across add/remove or create/update
operations. This is true for all standard images (those specified in
`toc_entries`) but not for those specified via the --blob option.
Xing Zheng [Tue, 14 Feb 2017 10:03:20 +0000 (18:03 +0800)]
rockchip: rk3399: enable secure accessing for SRAM
Sorry to miss the security configuration for SRAM, if we don't support
it, somebody may modify the comment of SRAM in the non-secure space.
Let's fix this issue.
Xing Zheng [Thu, 9 Feb 2017 06:51:38 +0000 (14:51 +0800)]
rockchip: rk3399: disable training modules after DDR DFS
On resume, we use the DFS hardware to switch frequency index,
followed by a full training sequence on that index. Leaving
the DFS training modules enabled causes issues with the full
training done at resume. We also only needs these enabled
during a call to ddr_set_rate during runtime, so there's no
issue disabling them at the end of ddr_set_rate.
Derek Basehore [Thu, 2 Feb 2017 02:09:13 +0000 (18:09 -0800)]
rockchip: rk3399: Move DQS drive strength setting to M0
This moves the setting of the DQS drive strength to the M0 to minimize
the impact on DDR transactions. We need to have the DQS drive strength
changed for data training, which is triggered by the M0, but it also
needs to be changed back when data training is finished.
Derek Basehore [Wed, 1 Feb 2017 00:37:01 +0000 (16:37 -0800)]
rockchip: rk3399: Remove dram dfs optimization
This removes an optimization to not recalculate parameters if the
frequency index being switched to hold the next frequency. This is
because some registers do not have a copy per frequency index, so this
optimization might be causing problems.
Derek Basehore [Tue, 31 Jan 2017 08:20:19 +0000 (00:20 -0800)]
rockchip: rk3399: Save and restore RX_CAL_DQS values
We were getting far off values on resume for the RX_CAL_DQS values.
This saves and restores the values for suspend/resume until the root
of the problem is figured out
Julius Werner [Tue, 31 Jan 2017 02:26:07 +0000 (18:26 -0800)]
rockchip: Add MIN() and MAX() macros back to M0 code
These macros were accidentally deleted in a previous cleanup. This
slipped through because the code using them is currently unused, but
that may change in the future.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Julius Werner [Tue, 31 Jan 2017 00:13:21 +0000 (16:13 -0800)]
rockchip: Clean up M0 Makefile, clarify float-abi
This patch shuffles the M0 Makefile flags around a bit trying to make
their purpose clearer and remove duplication. Since all three build
steps (compiling, assembling, linking) actually call GCC, remove the
misleading aliases $(AS) and $(LD) to avoid confusion that those tools
might be called directly. Split flags into a common group that has
meaning for all three steps and separate variables specific to each
step. Remove -nostartfiles which is a strict subset of -nostdlib.
Also add explicit parameters for -mfloat-abi=soft, -fomit-frame-pointer
and -fno-common. If omitted these settings depend on the toolchain's
built-in default and cause various problems if they resolve to
unexpected values.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Xing Zheng [Thu, 22 Dec 2016 10:34:14 +0000 (18:34 +0800)]
rockchip: rk3399: sperate the BL31 parameters for sharing
Maybe the coreboot will reference the BL31 parameters (e.g the TZRAM_BASE
and TZRAM_SIZE for DDR secure regions), we can split them and don't have
to hardcode the range in two places.
Xing Zheng [Fri, 24 Feb 2017 06:47:51 +0000 (14:47 +0800)]
rockchip: rk3399: configure the DDR secure region for BL31 image
Move the BL31 loaded base address 0x10000 to 0x1000, and configure
the the memory range 0~1MB is secure, the goal is that make sure
the BL31 image will be not modified.
Xing Zheng [Fri, 24 Feb 2017 08:26:11 +0000 (16:26 +0800)]
rockchip: Clean up header and referenced files
So far, there are more and more features are supported on the RK3399,
meanwhile, these features are increasingly being defined and intertwined.
It's time to clean up and make them clearer.
Derek Basehore [Mon, 9 Jan 2017 23:38:57 +0000 (15:38 -0800)]
rockchip: rk3399: Don't wait for vblank in M0 for ddrfreq
This removes waiting for vblank on the M0 during ddrfreq transitions.
That will now be done in the kernel to allow scheduling to be done on
the CPU core that changes the ddr frequency. Waiting for vblank in
the M0 would have the CPU core that waits on the M0 spin looping for
up to 16ms (1 frame for the display).
As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1
register, it need set the write_mask bit (bit16 ~ bit31), but as
we test, it not need it. So need to correct the setting way, otherwise
it will set wrong value to this register.
Xing Zheng [Tue, 20 Dec 2016 12:44:41 +0000 (20:44 +0800)]
FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init
We found that the DUT will be hanged if we don't set the bit_1 of the
PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1
is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the
TRM incorrect? We need to check it with the IC team and re-clean the
commit message and explain it tomorrow.
Lin Huang [Mon, 12 Dec 2016 07:18:08 +0000 (15:18 +0800)]
rockchip: rk3399: improve the m0 enable flow
This patch do following things:
1. Request hresetn_cm0s_pmu_req first then request
poresetn_cm0s_pmu_req during M0 enable.
2. Do not diable M0 clock for ddr dvfs.
3. Correct the clk_pmum0_gating_dis bit, it is BIT0 not BIT1
4. do not set/clear hclk_noc_pmu_en in M0 code, it does not relate
to the M0 clock.
Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org>
projects / arm-tf.git / log