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3 years agoMerge "fix(stm32mp1-fdts): correct memory mapping for STM32MP13" into integration
Madhukar Pappireddy [Tue, 17 May 2022 15:15:11 +0000 (17:15 +0200)]
Merge "fix(stm32mp1-fdts): correct memory mapping for STM32MP13" into integration

3 years agoMerge "refactor(security): upgrade tools to OpenSSL 3.0" into integration
Manish Pandey [Tue, 17 May 2022 14:48:07 +0000 (16:48 +0200)]
Merge "refactor(security): upgrade tools to OpenSSL 3.0" into integration

3 years agofix(stm32mp1-fdts): correct memory mapping for STM32MP13
Yann Gautier [Tue, 17 May 2022 14:21:25 +0000 (16:21 +0200)]
fix(stm32mp1-fdts): correct memory mapping for STM32MP13

On STM32MP13, OP-TEE will be loaded at the beginning of the secure
memory, and will be responsible for its shared memory.
The memory allocated to OP-TEE is then 32MB, and the shared memory
does no more appear in the STM32MP13 fw-config DT file.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I4e9238ddb4d82079b9ddf8fc8f6916b5b989d263

3 years agoMerge "fix(arm): remove reclamation of functions starting with "init"" into integration
Manish Pandey [Tue, 17 May 2022 09:11:16 +0000 (11:11 +0200)]
Merge "fix(arm): remove reclamation of functions starting with "init"" into integration

3 years agoMerge changes I2fcf13b7,I153ccb43 into integration
Madhukar Pappireddy [Mon, 16 May 2022 19:59:08 +0000 (21:59 +0200)]
Merge changes I2fcf13b7,I153ccb43 into integration

* changes:
  feat(n1sdp): add support for nt_fw_config
  feat(n1sdp): enable trusted board boot on n1sdp

3 years agorefactor(security): upgrade tools to OpenSSL 3.0
Juan Pablo Conde [Wed, 2 Mar 2022 23:10:08 +0000 (18:10 -0500)]
refactor(security): upgrade tools to OpenSSL 3.0

Host tools cert_tool and encrypt_fw refactored to be fully
compatible with OpenSSL v3.0.

Changes were made following the OpenSSL 3.0 migration guide:
https://www.openssl.org/docs/man3.0/man7/migration_guide.html
In some cases, those changes are straightforward and only
a small modification on the types or API calls was needed
(e.g.: replacing BN_pseudo_rand() with BN_rand(). Both identical
since v1.1.0).
The use of low level APIs is now deprecated. In some cases,
the new API provides a simplified solution for our goals and
therefore the code was simplified accordingly (e.g.: generating
RSA keys through EVP_RSA_gen() without the need of handling the
exponent). However, in some cases, a more
sophisticated approach was necessary, as the use of a context
object was required (e.g.: when retrieving the digest value from
an SHA file).

Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I978e8578fe7ab3e71307450ebe7e7812fbcaedb6

3 years agoMerge changes from topic "ffa_el3_spmc" into integration
Olivier Deprez [Mon, 16 May 2022 10:32:27 +0000 (12:32 +0200)]
Merge changes from topic "ffa_el3_spmc" into integration

* changes:
  feat(spmd): allow forwarding of FFA_FRAG_RX/TX calls
  feat(spmc): add support for FFA_SPM_ID_GET
  feat(spmc): add support for forwarding a secure interrupt to the SP
  feat(spmc): add support for FF-A power mgmt. messages in the EL3 SPMC

3 years agoMerge changes from topic "ffa_el3_spmc" into integration
Olivier Deprez [Mon, 16 May 2022 10:05:59 +0000 (12:05 +0200)]
Merge changes from topic "ffa_el3_spmc" into integration

* changes:
  feat(spmc): enable the SPMC to pass the linear core ID in a register
  feat(spmc): add FFA_RX_RELEASE handler
  feat(spmc): add FFA_RUN handler
  feat(spmc): support FFA_ID_GET ABI
  feat(spmc): add FFA_FEATURES handler
  feat(spmc): add FFA_PARTITION_INFO_GET handler
  feat(spmc): enable handling FF-A RX/TX Mapping ABIs
  docs(maintainers): introduce SPMC maintainer section

3 years agofeat(spmd): allow forwarding of FFA_FRAG_RX/TX calls
Marc Bonnici [Thu, 23 Sep 2021 08:44:14 +0000 (09:44 +0100)]
feat(spmd): allow forwarding of FFA_FRAG_RX/TX calls

Enable the SPMD to forward FFA_FRAG_RX/TX calls between
the normal world and the SPMC.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I097a48552827a8527dd3efe1155bc601d7cbf887

3 years agofeat(spmc): add support for FFA_SPM_ID_GET
Marc Bonnici [Thu, 25 Nov 2021 15:54:52 +0000 (15:54 +0000)]
feat(spmc): add support for FFA_SPM_ID_GET

Enable a Secure Partition to query the ID assigned to the SPMC.
The SPMD will take care of any calls from the normal world
therefore we should not need to handle this case in the SPMC.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I97903e920e928df385addbb2d383f24e602bf2db

3 years agoMerge changes If2408af3,If485ff27 into integration
Madhukar Pappireddy [Fri, 13 May 2022 16:13:33 +0000 (18:13 +0200)]
Merge changes If2408af3,If485ff27 into integration

* changes:
  feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
  feat(versal): add support to reset SGI

3 years agofeat(spmc): add support for forwarding a secure interrupt to the SP
Achin Gupta [Mon, 4 Oct 2021 19:17:45 +0000 (20:17 +0100)]
feat(spmc): add support for forwarding a secure interrupt to the SP

This patch adds support for forwarding a secure interrupt that
preempts the normal world to a SP for top-half interrupt handling.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Iaa6e96f4cf8922ba5b6d128a19359df15e44158d

3 years agoMerge changes from topic "ns/save_fpregs_context" into integration
Olivier Deprez [Fri, 13 May 2022 15:28:58 +0000 (17:28 +0200)]
Merge changes from topic "ns/save_fpregs_context" into integration

* changes:
  feat(sgi): enable fpregs context save and restore
  feat(spm_mm): add support to save and restore fp regs

3 years agofeat(spmc): enable the SPMC to pass the linear core ID in a register
Marc Bonnici [Wed, 15 Dec 2021 18:00:50 +0000 (18:00 +0000)]
feat(spmc): enable the SPMC to pass the linear core ID in a register

Add TF-A implementation defined behaviour to provide the linear core
ID in the x4 register when bringing up an SP.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I6cb215841097b264d252ec0262b0b7272be99d41

3 years agofeat(spmc): add support for FF-A power mgmt. messages in the EL3 SPMC
Marc Bonnici [Tue, 12 Apr 2022 16:18:13 +0000 (17:18 +0100)]
feat(spmc): add support for FF-A power mgmt. messages in the EL3 SPMC

This patch adds support for forwarding the following PSCI messages
received by the SPMC at EL3 to the S-EL1 SP if the SP has indicated
that it wishes to receive the appropriate message via its manifest.

1. A PSCI CPU_OFF message in response to a cpu hot unplug request
   from the OS.
2. A message to indicate warm boot of a cpu in response to a cpu
   hot plug request from the OS.
3. A PSCI CPU_SUSPEND message in response to a cpu idle event
   initiated from the OS.
4. A message to indicate warm boot of a cpu from a shallow power
   state in response to a cpu resume power event.

This patch also implements the FFA_SECONDARY_EP_REGISTER function to
enable the SP specify its secondary entrypoint.

Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I375d0655b2c6fc27445facc39213d1d0678557f4

3 years agofeat(spmc): add FFA_RX_RELEASE handler
Marc Bonnici [Tue, 12 Apr 2022 16:17:45 +0000 (17:17 +0100)]
feat(spmc): add FFA_RX_RELEASE handler

Enable a partition to release its RX buffer and the SPMC
to update the appropriate state tracking.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5fb6d92244b5ed5f032269b29b102aa874bf3ae3

3 years agofeat(spmc): add FFA_RUN handler
Marc Bonnici [Tue, 31 Aug 2021 16:57:04 +0000 (17:57 +0100)]
feat(spmc): add FFA_RUN handler

Enable the SPMC to handle the FFA_RUN ABI and update
the state tracking accordingly.

Change-Id: I3e8a3fa3ec9b03830055d2fbd6124b8ff1ed4103
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
3 years agofeat(spmc): support FFA_ID_GET ABI
Marc Bonnici [Wed, 24 Nov 2021 15:40:00 +0000 (15:40 +0000)]
feat(spmc): support FFA_ID_GET ABI

Allow for a partition to retrieve its own partition ID.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I1a19ac30b86736d818673c239b2f8fd2d6128c06

3 years agofeat(spmc): add FFA_FEATURES handler
Marc Bonnici [Mon, 13 Dec 2021 11:08:59 +0000 (11:08 +0000)]
feat(spmc): add FFA_FEATURES handler

Enable the spmc to report the features that it currently supports.
Populated with the currently implemented functionality.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I00e51ded284efd87cd50a0e9416dbc33f22ced85

3 years agofeat(spmc): add FFA_PARTITION_INFO_GET handler
Marc Bonnici [Tue, 17 Aug 2021 17:00:07 +0000 (18:00 +0100)]
feat(spmc): add FFA_PARTITION_INFO_GET handler

Enable the SPMC to handle calls to FFA_PARTITION_INFO_GET.
This allows the normal world to discover which partitions
are running in the secure world including logical partitions
in EL3.

This implementation supports both the v1.0 and v1.1
implementations of the Partition Info Get Descriptor.
The SPMC populates the appropriate descriptor in the
partitions RX buffer, if requested, according to the
version of FF-A that the caller is using.

Additionally rename the common/uuid UUID_H include guard
due to a conflict with another header file.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I0a85f1dae50fae1fe47a3cafb765fbe9f40619e1

3 years agofeat(spmc): enable handling FF-A RX/TX Mapping ABIs
Marc Bonnici [Wed, 25 Aug 2021 11:09:37 +0000 (12:09 +0100)]
feat(spmc): enable handling FF-A RX/TX Mapping ABIs

Enable handling of FFA_RXTX_MAP and FFA_RXTX_UNMAP ABIs
and ensure these buffers are mapped as required to allow
access by the SPMC.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ifc425f1ee16c90d1d95b6ae4ac9992d6f785227b

3 years agoMerge changes from topic "rss/mboot-attest" into integration
Sandrine Bailleux [Fri, 13 May 2022 14:15:35 +0000 (16:15 +0200)]
Merge changes from topic "rss/mboot-attest" into integration

* changes:
  docs(maintainers): add PSA, MHU, RSS comms code owners
  feat(plat/arm/fvp): enable RSS backend based measured boot
  feat(lib/psa): mock PSA APIs
  feat(drivers/measured_boot): add RSS backend
  feat(drivers/arm/rss): add RSS communication driver
  feat(lib/psa): add initial attestation API
  feat(lib/psa): add measured boot API
  feat(drivers/arm/mhu): add MHU driver

3 years agoMerge changes I50721040,I1ce4b7b4,I9658aef7,I40ff55eb into integration
Joanna Farley [Fri, 13 May 2022 12:29:24 +0000 (14:29 +0200)]
Merge changes I50721040,I1ce4b7b4,I9658aef7,I40ff55eb into integration

* changes:
  fix(intel): remove unused printout
  fix(intel): fix configuration status based on start request
  style(intel): align the sequence in header file
  fix(intel): remove redundant NOC header declarations

3 years agodocs(maintainers): add PSA, MHU, RSS comms code owners
David Vincze [Thu, 12 May 2022 14:07:03 +0000 (16:07 +0200)]
docs(maintainers): add PSA, MHU, RSS comms code owners

Adding Sandrine Bailleux for the PSA APIs and myself for the
MHU and RSS comms drivers as code owner.

Change-Id: Ib948479cc6e46163aae59c938877a2d0bcf91754
Signed-off-by: David Vincze <david.vincze@arm.com>
3 years agofix(intel): remove unused printout
Sieu Mun Tang [Fri, 13 May 2022 08:42:42 +0000 (16:42 +0800)]
fix(intel): remove unused printout

This patch is to remove unused printout.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I507210402dcbaf8369209308ae1fcedaccb0292d

3 years agofix(intel): fix configuration status based on start request
Sieu Mun Tang [Fri, 13 May 2022 06:55:05 +0000 (14:55 +0800)]
fix(intel): fix configuration status based on start request

This patch is to fix configuration status command now returns
the result based on the last config start command made to the
runtime software. The status type can be either:
- NO_REQUEST (default)
- RECONFIGURATION
- BITSTREAM_AUTH

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1ce4b7b4c741d88de88778f8fbed7dfe83a39fbc

3 years agostyle(intel): align the sequence in header file
Sieu Mun Tang [Fri, 13 May 2022 06:36:32 +0000 (14:36 +0800)]
style(intel): align the sequence in header file

This patch is to align the sequence of function in header file.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9658aef78b06b744c6c14f95b2821daf5dbb0082

3 years agofix(intel): remove redundant NOC header declarations
Sieu Mun Tang [Fri, 13 May 2022 03:14:08 +0000 (11:14 +0800)]
fix(intel): remove redundant NOC header declarations

This patch is to remove redundant NOC declarations in
system manager header file. The NOC headers are shareable
across both Stratix 10 and Agilex platforms.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I40ff55eb1d8fe280db1d099d5d1a3c2bf4b4b459

3 years agofeat(versal): add SMCCC call TF_A_PM_REGISTER_SGI
Tanmay Shah [Tue, 14 Dec 2021 12:53:40 +0000 (04:53 -0800)]
feat(versal): add SMCCC call TF_A_PM_REGISTER_SGI

This call is used to register and reset SGI interrupt.
Before this functionality was performed using IOCTL_REGISTER_SGI
pm_ioctl EEMI call. It's not correct use of PM_IOCTL as it is
not EEMI functionality. Instead this new SMCCC call will be
handled by TF-A specific handler.

Change-Id: If2408af38b889d29a5c584e8eec5f1672eab4fb5
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
3 years agofeat(versal): add support to reset SGI
Venkatesh Yadav Abbarapu [Mon, 19 Apr 2021 13:49:57 +0000 (07:49 -0600)]
feat(versal): add support to reset SGI

Add "reset" parameter in pm_register_sgi() to reset
SGI number. This will be required if OS wants to reset
SGI number to default state. Caller can reset param to
1 to reset SGI in ATF.

Change-Id: If485ff275df884f74eb67671cac7fa953458afe9
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
3 years agoMerge "fix(security): workaround for CVE-2022-23960" into integration
Madhukar Pappireddy [Thu, 12 May 2022 18:24:10 +0000 (20:24 +0200)]
Merge "fix(security): workaround for CVE-2022-23960" into integration

3 years agofeat(n1sdp): add support for nt_fw_config
sahil [Tue, 15 Mar 2022 08:41:43 +0000 (14:11 +0530)]
feat(n1sdp): add support for nt_fw_config

This patch adds support to load nt_fw_config with the information from
plat_info sds structure which is then passed from BL2 to BL33.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I2fcf13b7bf5ab042ef830157fd9cceedbdca617a

3 years agofeat(n1sdp): enable trusted board boot on n1sdp
sah01 [Sun, 6 Jun 2021 09:08:01 +0000 (14:38 +0530)]
feat(n1sdp): enable trusted board boot on n1sdp

Move from RESET_TO_BL31 boot to a TBBR style boot on N1sdp.

Signed-off-by: sahil <sahil@arm.com>
Change-Id: I153ccb43a4a013830973c7a183825d62b372c65e

3 years agoMerge "docs(versal): fix the versal platform emu name" into integration
Madhukar Pappireddy [Thu, 12 May 2022 14:49:36 +0000 (16:49 +0200)]
Merge "docs(versal): fix the versal platform emu name" into integration

3 years agoMerge "fix(errata): workaround for DSU-110 erratum 2313941" into integration
Madhukar Pappireddy [Thu, 12 May 2022 14:34:40 +0000 (16:34 +0200)]
Merge "fix(errata): workaround for DSU-110 erratum 2313941" into integration

3 years agoMerge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
Madhukar Pappireddy [Thu, 12 May 2022 14:19:15 +0000 (16:19 +0200)]
Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration

* changes:
  fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
  fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
  fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
  fix(intel): extending to support large file size for AES encryption and decryption
  feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
  feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
  fix(intel): update certificate mask for FPGA Attestation
  feat(intel): update to support maximum response data size
  feat(intel): support ECDSA HASH Verification
  feat(intel): support ECDSA HASH Signing
  feat(intel): support ECDH request
  feat(intel): support ECDSA SHA-2 Data Signature Verification
  feat(intel): support ECDSA SHA-2 Data Signing
  feat(intel): support ECDSA Get Public Key
  feat(intel): support session based SDOS encrypt and decrypt
  feat(intel): support AES Crypt Service
  feat(intel): support HMAC SHA-2 MAC verify request
  feat(intel): support SHA-2 hash digest generation on a blob
  feat(intel): support extended random number generation
  feat(intel): support crypto service key operation
  feat(intel): support crypto service session
  feat(intel): extend attestation service to Agilex family
  fix(intel): flush dcache before sending certificate to mailbox
  fix(intel): introduce a generic response error code
  fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
  feat(intel): single certificate feature enablement
  feat(intel): initial commit for attestation service
  fix(intel): update encryption and decryption command logic

3 years agoMerge "fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1" into integration
Madhukar Pappireddy [Thu, 12 May 2022 14:14:55 +0000 (16:14 +0200)]
Merge "fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1" into integration

3 years agofix(arm): remove reclamation of functions starting with "init"
Manish Pandey [Wed, 11 May 2022 14:43:54 +0000 (15:43 +0100)]
fix(arm): remove reclamation of functions starting with "init"

When RECLAIM_INIT_CODE is enabled, functions with __init attribute can
be reclaimed after boot and marked as Execute Never.
Because of a bug in linker script the functions starting with "init"
were also marked XN and causing instruction abort.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2221973c05af170acf4e723cd44645b9ff9d58d2

3 years agofix(security): workaround for CVE-2022-23960
Bipin Ravi [Fri, 6 May 2022 21:02:30 +0000 (16:02 -0500)]
fix(security): workaround for CVE-2022-23960

Implements the loop workaround for Cortex Makalu/Makalu-ELP/Hunter
and Neoverse Demeter/Poseidon.

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f6689b662ecac92491e0c0902df4270051ce5b

3 years agofix(errata): workaround for DSU-110 erratum 2313941
Bipin Ravi [Wed, 22 Dec 2021 20:35:21 +0000 (14:35 -0600)]
fix(errata): workaround for DSU-110 erratum 2313941

DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions
r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open.

The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable
clock gating of the SCLK domain. This will increase the idle power
consumption.

This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1781796/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I54d948b23e8e01aaf1898ed9fe4e2255dd209318
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
3 years agofeat(sgi): enable fpregs context save and restore
Nishant Sharma [Tue, 19 Apr 2022 09:23:59 +0000 (10:23 +0100)]
feat(sgi): enable fpregs context save and restore

This is required to prevent Nwd context corruption during StMM
execution.

Standalone MM uses OpenSSL for secure boot, which uses FP registers for
floating point calculations.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I6ed11d4fa5d64c3089a24b66fd048a841c480792

3 years agofeat(spm_mm): add support to save and restore fp regs
Nishant Sharma [Tue, 19 Apr 2022 09:16:48 +0000 (10:16 +0100)]
feat(spm_mm): add support to save and restore fp regs

Add the support to save Nwd's floating point registers before switching
to SEL0 and then restore it after coming out of it. Emit a warning
message if SPM_MM is built with CTX_INCLUDE_FPREGS == 0

There is no need to save FP registers of SEL0 because secure partitions
run to completion.

This change is used to prevent context corruption if secure partition
enabled and Nwd decide to use floating point registers.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I1eea16ea2311a4f00a806ea72c118752821b9abb

3 years agoMerge changes from topic "fix_st_spi" into integration
Madhukar Pappireddy [Wed, 11 May 2022 15:31:44 +0000 (17:31 +0200)]
Merge changes from topic "fix_st_spi" into integration

* changes:
  fix(st-spi): remove SR_BUSY bit check before sending command
  fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()

3 years agoMerge "docs: update release and code freeze dates" into integration
Madhukar Pappireddy [Wed, 11 May 2022 15:16:48 +0000 (17:16 +0200)]
Merge "docs: update release and code freeze dates" into integration

3 years agoMerge "fix(security): workaround for CVE-2022-23960 for Cortex-X1" into integration
Bipin Ravi [Wed, 11 May 2022 14:59:15 +0000 (16:59 +0200)]
Merge "fix(security): workaround for CVE-2022-23960 for Cortex-X1" into integration

3 years agoMerge "fix(errata): workarounds for cortex-x1 errata" into integration
Bipin Ravi [Wed, 11 May 2022 14:59:00 +0000 (16:59 +0200)]
Merge "fix(errata): workarounds for cortex-x1 errata" into integration

3 years agoMerge "feat(cpu): add support for Cortex-X1" into integration
Bipin Ravi [Wed, 11 May 2022 14:58:50 +0000 (16:58 +0200)]
Merge "feat(cpu): add support for Cortex-X1" into integration

3 years agofeat(plat/arm/fvp): enable RSS backend based measured boot
Tamas Ban [Fri, 11 Feb 2022 08:49:36 +0000 (09:49 +0100)]
feat(plat/arm/fvp): enable RSS backend based measured boot

Enable the RSS backend based measured boot feature.
In the absence of RSS the mocked version of PSA APIs
are used. They always return with success and hard-code data.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I7543e9033a7a21f1b836d911d8d9498c6e09b956

3 years agofeat(lib/psa): mock PSA APIs
Tamas Ban [Tue, 18 Jan 2022 15:20:47 +0000 (16:20 +0100)]
feat(lib/psa): mock PSA APIs

Introduce PLAT_RSS_NOT_SUPPORTED build config to
provide a mocked version of PSA APIs. The goal is
to test the RSS backend based measured boot and
attestation token request integration on such
a platform (AEM FVP) where RSS is otherwise
unsupported. The mocked PSA API version does
not send a request to the RSS, it only returns
with success and hard-coded values.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ice8d174adf828c1df08fc589f0e17abd1e382a4d

3 years agofeat(drivers/measured_boot): add RSS backend
Tamas Ban [Tue, 11 Jan 2022 19:24:24 +0000 (20:24 +0100)]
feat(drivers/measured_boot): add RSS backend

Runtime Security Subsystem (RSS) provides for the host:
- Runtime service to store measurments, which were
  computed by the host during measured boot.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Ia9e4e8a1fe8f01a28da1fd8c434b780f2a08f94e

3 years agofeat(drivers/arm/rss): add RSS communication driver
Tamas Ban [Tue, 18 Jan 2022 15:32:18 +0000 (16:32 +0100)]
feat(drivers/arm/rss): add RSS communication driver

This commit adds a driver to conduct the AP's communication
with the Runtime Security Subsystem (RSS).
RSS is Arm's reference implementation for the CCA HES [1].
It can be considered as a secure enclave to which, for example,
certain services can be offloaded such as initial attestation.

RSS comms driver:
 - Relies on MHU v2.x communication IP, using a generic MHU API,
 - Exposes the psa_call(..) API to the upper layers.

[1] https://developer.arm.com/documentation/DEN0096/latest

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: Ib174ac7d1858834006bbaf8aad0eb31e3a3ad107

3 years agofeat(lib/psa): add initial attestation API
Tamas Ban [Fri, 11 Feb 2022 14:24:05 +0000 (15:24 +0100)]
feat(lib/psa): add initial attestation API

Supports:
 - Get Platform Attestation token from secure enclave

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Icaeb7b4eaff08e10f449fbf752068de3ac7974bf

3 years agofeat(lib/psa): add measured boot API
Tamas Ban [Tue, 18 Jan 2022 15:19:17 +0000 (16:19 +0100)]
feat(lib/psa): add measured boot API

A secure enclave could provide an alternate
backend for measured boot. This API can be used
to store measurements in a secure enclave, which
provides the measured boot runtime service.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I2448e324e7ece6b318403c5937dfe7abea53d0f3

3 years agofeat(drivers/arm/mhu): add MHU driver
Tamas Ban [Mon, 10 Jan 2022 16:04:03 +0000 (17:04 +0100)]
feat(drivers/arm/mhu): add MHU driver

The Arm Message Handling Unit (MHU) is a mailbox controller used to
communicate with other processing element(s). Adding a driver to
enable the communication:
- Adding generic MHU driver interface,
- Adding MHU_v2_x driver.

Driver supports:
 - Discovering available MHU channels,
 - Sending / receiving words over MHU channels,
 - Signaling happens over a dedicated channel.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: I41a5b968f6b8319cdbdf7907d70bd8837839862e

3 years agofix(security): workaround for CVE-2022-23960 for Cortex-X1
Okash Khawaja [Thu, 21 Apr 2022 12:15:56 +0000 (13:15 +0100)]
fix(security): workaround for CVE-2022-23960 for Cortex-X1

Implements the loop workaround for Cortex-X1.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I5828a26c1ec3cfb718246ea5c3b099dabc0fb3d7

3 years agofix(errata): workarounds for cortex-x1 errata
Okash Khawaja [Thu, 21 Apr 2022 11:20:21 +0000 (12:20 +0100)]
fix(errata): workarounds for cortex-x1 errata

This patch adds workarounds for following cortex-x1 errata:

1821534 (CatB)
1688305 (CatB)
1827429 (CatB)

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401782/latest

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I10ebe8d5c56a6d273820bb2c682f21bf98daa7a5

3 years agofeat(cpu): add support for Cortex-X1
Okash Khawaja [Thu, 21 Apr 2022 09:59:34 +0000 (10:59 +0100)]
feat(cpu): add support for Cortex-X1

This patch adds basic CPU library code to support Cortex-X1 CPU in TF-A.
Follow-up patches will add selected errata workarounds for this CPU.

Signed-off-by: Okash Khawaja <okash@google.com>
Change-Id: I4a3d50a98bf55a555bfaefeed5c7b88a35e3bc21

3 years agodocs: update release and code freeze dates
Daniel Boulby [Mon, 9 May 2022 10:11:49 +0000 (11:11 +0100)]
docs: update release and code freeze dates

Change-Id: I72d200a0cfbcb4ef53b732faa5b7125dce91395d
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
3 years agofix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
Sieu Mun Tang [Tue, 10 May 2022 15:17:04 +0000 (23:17 +0800)]
fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD

This patch is to add flash dcache after return
response in INTEL_SIP_SMC_MBOX_SEND_CMD.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie9451e352f2b7c41ebb44a1f6be9da35f4600fb9

3 years agofix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
Sieu Mun Tang [Thu, 28 Apr 2022 08:28:48 +0000 (16:28 +0800)]
fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying

This patch is to extend to support large file size
for SHA2/HMAC get digest and verifying. The large
file will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1815deeb61287b32c3e77c5ac1b547b79ef12674

3 years agofix(intel): extending to support large file size for SHA-2 ECDSA data signing and...
Sieu Mun Tang [Thu, 28 Apr 2022 08:23:20 +0000 (16:23 +0800)]
fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying

This patch is to extend to support large file size
for SHA-2 ECDSA data signing and signature verifying.
The large file will be split into smaller chunk and
send using initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: If277b2b375a404fe44b0858006c8ba6316a5ce23

3 years agofix(intel): extending to support large file size for AES encryption and decryption
Sieu Mun Tang [Thu, 28 Apr 2022 08:15:54 +0000 (16:15 +0800)]
fix(intel): extending to support large file size for AES encryption and decryption

This patch is to extend to support large file size
for AES encryption and decryption. The large file
will be split into smaller chunk and send using
initialize, update and finalize staging method.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie2ceaf247e0d7082aad84faf399fbd18d129c36a

3 years agofeat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
Sieu Mun Tang [Tue, 10 May 2022 15:26:57 +0000 (23:26 +0800)]
feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands

A separated SMC function ID of mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7996d5054f76c139b5ad55451c373f5669a1017f

3 years agofeat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
Sieu Mun Tang [Wed, 11 May 2022 02:45:19 +0000 (10:45 +0800)]
feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands

A separated SMC function ID of non-mailbox command
is introduced for the new format of SMC protocol.

The new format of SMC procotol will be started
using by Zephyr.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I01cff2739364b1bda2ebb9507ddbcef6095f5d29

3 years agofix(intel): update certificate mask for FPGA Attestation
Boon Khai Ng [Mon, 30 Aug 2021 07:05:49 +0000 (15:05 +0800)]
fix(intel): update certificate mask for FPGA Attestation

Update the certificate mask to 0xff to cover all certificate
in Agilex family.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id40bc3aa4b3e4f7568a58581bbb03a75b0f20a0b

3 years agofeat(intel): update to support maximum response data size
Sieu Mun Tang [Wed, 11 May 2022 02:23:13 +0000 (10:23 +0800)]
feat(intel): update to support maximum response data size

Update to support maximum (4092 bytes) response data size.
And, clean up the intel_smc_service_completed function to
directly write the response data to addr to avoid additional
copy.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I0a230e73c563d22e6999ad3473587b07382dacfe

3 years agofeat(intel): support ECDSA HASH Verification
Sieu Mun Tang [Tue, 10 May 2022 09:53:32 +0000 (17:53 +0800)]
feat(intel): support ECDSA HASH Verification

Supporting the command to send digital signature verification
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic86f531bfe7cc7606699f2b064ac677aaf806a76

3 years agofeat(intel): support ECDSA HASH Signing
Sieu Mun Tang [Tue, 10 May 2022 09:50:30 +0000 (17:50 +0800)]
feat(intel): support ECDSA HASH Signing

Supporting the command to send digital signature signing
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I12cf0f1ceaf07c33a110eae398d3ad82a9b13d38

3 years agofeat(intel): support ECDH request
Sieu Mun Tang [Tue, 10 May 2022 09:48:11 +0000 (17:48 +0800)]
feat(intel): support ECDH request

This command sends the request on generating a share secret on
Diffie-Hellman key exchange.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic7c8470cf036ea8c17bf87401f49936950b3e1d6

3 years agofeat(intel): support ECDSA SHA-2 Data Signature Verification
Sieu Mun Tang [Wed, 11 May 2022 02:16:40 +0000 (10:16 +0800)]
feat(intel): support ECDSA SHA-2 Data Signature Verification

This command support ECC based signature verification on a blob.
Supported ECC algorithm are NISP P-256, NISP P-384, Brainpool 256
and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I7f43d2a69bbe6693ec1bb90f32b817cf00f9f5ae

3 years agofeat(intel): support ECDSA SHA-2 Data Signing
Sieu Mun Tang [Tue, 10 May 2022 09:39:26 +0000 (17:39 +0800)]
feat(intel): support ECDSA SHA-2 Data Signing

This command support ECC based signing on a blob. Supported ECC algorithm
are NISP P-256, NISP P-384, Brainpool 256 and Brainpool 384.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I82f95ddafa6b62f8cd882fce9a3e63e469c85067

3 years agofeat(intel): support ECDSA Get Public Key
Sieu Mun Tang [Tue, 10 May 2022 09:36:32 +0000 (17:36 +0800)]
feat(intel): support ECDSA Get Public Key

To support the ECDSA feature and send the command
as a request to get the public key

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9d7bb5b6ab8ef7d4f3ceb21ff0068baf3175a1ac

3 years agofeat(intel): support session based SDOS encrypt and decrypt
Sieu Mun Tang [Mon, 9 May 2022 08:05:58 +0000 (16:05 +0800)]
feat(intel): support session based SDOS encrypt and decrypt

Extends existing Secure Data Object Service (SDOS) encryption and
decryption mailbox command to include session id and context id. The
new format requires an opened crypto service session.

A separated SMC function ID is introduced for the new format and it is
only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I2627750e8337c1af66217e9cb45981a9e06e7d19

3 years agofeat(intel): support AES Crypt Service
Sieu Mun Tang [Tue, 10 May 2022 09:30:00 +0000 (17:30 +0800)]
feat(intel): support AES Crypt Service

Enable Support for AES Crypt Service to send request
to encrypt or decrypt a blob. Command will send a memory
location that SDM will read and also memory location that
SDM will write back after encryption or decryption operation.
Response will be sent back after the crypto operation is done,
and data is written back to the destination

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86ea4ff64dda2fbb1000591e30fa8cb2640ce954

3 years agofeat(intel): support HMAC SHA-2 MAC verify request
Sieu Mun Tang [Tue, 10 May 2022 09:27:12 +0000 (17:27 +0800)]
feat(intel): support HMAC SHA-2 MAC verify request

This command sends request on checking the integrity and authenticity
of a blob by comparing the calculated MAC with tagged MAC. The
comparison result will be returned in response.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ifefdf67f088d7612d2ec2459d71faf2ec8181222

3 years agofeat(intel): support SHA-2 hash digest generation on a blob
Sieu Mun Tang [Tue, 10 May 2022 09:24:05 +0000 (17:24 +0800)]
feat(intel): support SHA-2 hash digest generation on a blob

This command is to request the SHA-2 hash digest on a blob.
If input has a key, the output shall be key-hash digest.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I08cb82d89a8e8f7bfe04f5f01e079ea49fe38cf5

3 years agofeat(intel): support extended random number generation
Sieu Mun Tang [Tue, 10 May 2022 09:18:19 +0000 (17:18 +0800)]
feat(intel): support extended random number generation

The random number generation (RNG) mailbox command format
is updated to extends the support to upto 4080 bytes random
number generation. The new RNG format requires an opened
crypto service session.

A separated SMC function ID is introduced for the new RNG
format and it is only supported by Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3f044a3c01ff7cb50be4705e2c1f982bf6f61432

3 years agodocs(maintainers): introduce SPMC maintainer section
Marc Bonnici [Mon, 14 Feb 2022 18:31:11 +0000 (18:31 +0000)]
docs(maintainers): introduce SPMC maintainer section

Renamed the existing SPM entry to the SPMD and add myself
as the SPMC maintainer.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ic74659b119986df5fc229a4470049d289eeef21a

3 years agodocs(versal): fix the versal platform emu name
Venkatesh Yadav Abbarapu [Wed, 11 May 2022 08:16:28 +0000 (13:46 +0530)]
docs(versal): fix the versal platform emu name

Fix the versal platform emu itr6 name.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Id9f3272c85513d8258fbbb3bd719c032053b3ada

3 years agofix(st-spi): remove SR_BUSY bit check before sending command
Christophe Kerello [Wed, 4 May 2022 09:28:15 +0000 (11:28 +0200)]
fix(st-spi): remove SR_BUSY bit check before sending command

Waiting for SR_BUSY bit when receiving a new command is not needed.
SR_BUSY bit is already managed in the previous command treatment.

Change-Id: I736e8488d354cb165ae765022d864cca1dbdc9ee
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
3 years agofix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
Christophe Kerello [Wed, 4 May 2022 09:14:55 +0000 (11:14 +0200)]
fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()

Currently, SR_TCF flag is checked in case there is data, this criteria
is not correct.

SR_TCF flags is set when programmed number of bytes have been
transferred to the memory device ("bytes" comprised command and data
send to the SPI device).
So even if there is no data, we must check SR_TCF flag.

Change-Id: I99c4145e639c1b842feb3690dd78329179c18132
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
3 years agofeat(intel): support crypto service key operation
Sieu Mun Tang [Mon, 9 May 2022 06:16:14 +0000 (14:16 +0800)]
feat(intel): support crypto service key operation

Support crypto service key operation mailbox commands through SMC.

Crypto service key operation begin by sending an open crypto service
session request to SDM firmware. Once successfully open the session,
send crypto service key management commands (import, export, remove
and get key info) with the associated session id to SDM firmware.
The crypto service key is required before perform any crypto service
(encryption, signing, etc). Last, close the session after finishes
crypto service. All crypto service keys associated with this session
will be erased by SDM firmware.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I02406533f38b9607eb1ec7e1395b9dc2d084a9e3

3 years agofeat(intel): support crypto service session
Sieu Mun Tang [Mon, 9 May 2022 04:08:42 +0000 (12:08 +0800)]
feat(intel): support crypto service session

Support crypto service open and close session mailbox commands through
SMC.

Crypto service support begin by sending an open crypto service session
request to SDM firmware. Last, close the session after finishes crypto
service. All crypto service parameters with this session will be erased
by SDM firmware.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I48968498bbd6f2e71791f4ed38dd5f369e171082

3 years agofeat(intel): extend attestation service to Agilex family
Sieu Mun Tang [Mon, 9 May 2022 02:48:53 +0000 (10:48 +0800)]
feat(intel): extend attestation service to Agilex family

This patch extends the functionality of FPGA Crypto Services (FCS) to
support FPGA Attestation feature in Agilex device.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3c2e29d2fa04d394e9f65d8143d7f4e57389cd02

3 years agofix(intel): flush dcache before sending certificate to mailbox
Boon Khai Ng [Tue, 25 May 2021 17:50:34 +0000 (01:50 +0800)]
fix(intel): flush dcache before sending certificate to mailbox

Due to the cache coherency issue the dcache need to flush
before sending the certificate to the mailbox

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I39d5144519d9c7308597698b4cbea1b8aba0a849

3 years agofix(intel): introduce a generic response error code
Sieu Mun Tang [Tue, 12 Apr 2022 07:00:13 +0000 (15:00 +0800)]
fix(intel): introduce a generic response error code

This patch will introduce a generic error code (0x3ff)
to be used in case where Secure Device Manager (SDM)
mailbox request is not failing (returns OK with no error
code) but BL31 instead wants to return error/reject
to the calling software. This value aligns with generic
error code implemented in SDM for consistency.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9894c7df8897fff9aa80970940a6f3f6bfa30bb7

3 years agofix(intel): allow non-secure access to FPGA Crypto Services (FCS)
Sieu Mun Tang [Fri, 6 May 2022 16:50:37 +0000 (00:50 +0800)]
fix(intel): allow non-secure access to FPGA Crypto Services (FCS)

Allows non-secure software to access FPGA Crypto Services (FCS)
through secure monitor calls (SMC).

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I805b3f650abf5e118e2c55e469866d5d0ca68048

3 years agofeat(intel): single certificate feature enablement
Sieu Mun Tang [Wed, 11 May 2022 02:01:54 +0000 (10:01 +0800)]
feat(intel): single certificate feature enablement

Extend the functionality of FPGA Crypto Service
(FCS) to support FPGA single certificate feature
so that the counter value can be updated with
only one preauthorized certificate

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibde87e4ee46367cf7f27f7bb0172838ab8766340

3 years agofeat(intel): initial commit for attestation service
Sieu Mun Tang [Wed, 11 May 2022 01:59:55 +0000 (09:59 +0800)]
feat(intel): initial commit for attestation service

This is to extend the functionality of FPGA Crypto Service (FCS)
to support FPGA Attestation feature in Stratix 10 device.

Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ib15783383dc9a06a2f0dc6dc1786f44b89f32cb1

3 years agofix(intel): update encryption and decryption command logic
Sieu Mun Tang [Wed, 11 May 2022 01:49:25 +0000 (09:49 +0800)]
fix(intel): update encryption and decryption command logic

This change is to re-align HPS cryption logic with
underlying Secure Device Manager's (SDM) mailbox API.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I8fc90982d3cddceaf401c1a112ff8e20861bf4c5

3 years agoMerge "fix(errata): workaround for Cortex-A710 erratum 2008768" into integration
Bipin Ravi [Tue, 10 May 2022 20:49:06 +0000 (22:49 +0200)]
Merge "fix(errata): workaround for Cortex-A710 erratum 2008768" into integration

3 years agoMerge "fix(errata): workaround for Cortex-A78 erratum 2395406" into integration
Bipin Ravi [Tue, 10 May 2022 20:40:55 +0000 (22:40 +0200)]
Merge "fix(errata): workaround for Cortex-A78 erratum 2395406" into integration

3 years agoMerge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disab...
Madhukar Pappireddy [Tue, 10 May 2022 18:17:51 +0000 (20:17 +0200)]
Merge "feat(intel): add support for F2S and S2F bridge SMC with mask to enable, disable and reset bridge" into integration

3 years agoMerge "fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72" into...
Bipin Ravi [Tue, 10 May 2022 14:49:08 +0000 (16:49 +0200)]
Merge "fix(security): report CVE 2022 23960 missing for aarch32 A57 and A72" into integration

3 years agoMerge "feat(snprintf): add support for length specifiers" into integration
Madhukar Pappireddy [Tue, 10 May 2022 14:27:21 +0000 (16:27 +0200)]
Merge "feat(snprintf): add support for length specifiers" into integration

3 years agoMerge "fix(errata): workaround for Cortex-A78 erratum 2376745" into integration
Joanna Farley [Tue, 10 May 2022 13:57:27 +0000 (15:57 +0200)]
Merge "fix(errata): workaround for Cortex-A78 erratum 2376745" into integration

3 years agoMerge "fix(amu): limit virtual offset register access to NS world" into integration
Joanna Farley [Tue, 10 May 2022 13:55:05 +0000 (15:55 +0200)]
Merge "fix(amu): limit virtual offset register access to NS world" into integration

3 years agoMerge changes from topic "ffa_el3_spmc" into integration
Olivier Deprez [Tue, 10 May 2022 13:18:36 +0000 (15:18 +0200)]
Merge changes from topic "ffa_el3_spmc" into integration

* changes:
  feat(spmc): add helper to obtain a partitions FF-A version
  feat(spmd): enable SPMD to forward FFA_VERSION to EL3 SPMC
  feat(spmc): enable handling FFA_VERSION ABI
  feat(spmc): add helper function to obtain endpoint mailbox
  feat(spmc): add helper function to obtain hyp structure
  feat(spmc): enable parsing of messaging methods from manifest

3 years agoMerge "fix(st): add missing header include" into integration
Manish Pandey [Tue, 10 May 2022 12:36:46 +0000 (14:36 +0200)]
Merge "fix(st): add missing header include" into integration

3 years agoMerge "fix(cm): add barrier before el3 ns exit" into integration
Olivier Deprez [Tue, 10 May 2022 12:15:51 +0000 (14:15 +0200)]
Merge "fix(cm): add barrier before el3 ns exit" into integration