Biwen Li [Mon, 11 Jan 2021 03:11:44 +0000 (11:11 +0800)]
fix(layerscape): fix build issue of mmap_add_ddr_region_dynamically
Fix build issue of mmap_add_ddr_region_dynamically():
ls_bl2_el3_setup.c:(.text.bl2_plat_preload_setup+0x28): undefined
reference to mmap_add_ddr_region_dynamically
Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I74a8b4c2337fc0646d6acb16ce61755c5efbdf38
Soby Mathew [Tue, 22 Mar 2022 13:58:52 +0000 (13:58 +0000)]
refactor(rme): reorg existing RMMD EL3 service FIDs
This patch reworks the GTSI service implementation in RMMD
such that it is made internal to RMMD. This rework also
lays the ground work for additional RMMD services which
can be invoked from RMM.
The rework renames some of the FID macros to make it
more suited for adding more RMMD services. All the RMM-EL31
service SMCs are now routed via rmmd_rmm_el3_handler().
Manish Pandey [Tue, 22 Mar 2022 15:42:16 +0000 (16:42 +0100)]
Merge changes from topic "stm32mp13" into integration
* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(stm32mp1-fdts): add DDR support for STM32MP13
feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
feat(stm32mp1): updates for STM32MP13 device tree compilation
feat(stm32mp1-fdts): add DT files for STM32MP13
feat(dt-bindings): add TZC400 bindings for STM32MP13
feat(stm32mp1): add "Boot mode" management for STM32MP13
feat(stm32mp1): manage HSLV on STM32MP13
feat(stm32mp1): add sdmmc compatible in platform define
feat(st-sdmmc2): allow compatible to be defined in platform code
feat(stm32mp1): update IO compensation on STM32MP13
feat(stm32mp1): call pmic_voltages_init() in platform init
feat(st-pmic): add pmic_voltages_init() function
feat(stm32mp1): update CFG0 OTP for STM32MP13
feat(stm32mp1): usb descriptor update for STM32MP13
feat(st-clock): add clock driver for STM32MP13
feat(dt-bindings): add bindings for STM32MP13
feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
feat(stm32mp1): use only one filter for TZC400 on STM32MP13
feat(stm32mp1): add a second fixed regulator
feat(stm32mp1): adaptations for STM32MP13 image header
feat(stm32mp1): update boot API for header v2.0
feat(stm32mp1): update IP addresses for STM32MP13
feat(stm32mp1): add part numbers for STM32MP13
feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
feat(stm32mp1): remove unsupported features on STM32MP13
feat(stm32mp1): update memory mapping for STM32MP13
feat(stm32mp1): introduce new flag for STM32MP13
feat(st): update stm32image tool for header v2
feat(stm32mp1): select platform compilation either by flag or DT
To choose either STM32MP13 or STM32MP15, one of the two flags can be
set to 1 in the make command line. Or the platform selection can be
done with device tree name, if it begins with stm32mp13 or stm32mp15.
Nicolas Le Bayon [Tue, 12 Jan 2021 17:18:27 +0000 (18:18 +0100)]
feat(stm32mp1-fdts): add DDR support for STM32MP13
Add dedicated device tree files for STM32MP13.
Add new DDR compatible for STM32MP13x.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Change-Id: Ib1bb9ad8cb2ab9f5f81549635d6604093aeb99d3
Yann Gautier [Tue, 25 Feb 2020 14:14:52 +0000 (15:14 +0100)]
feat(stm32mp1-fdts): add DT files for STM32MP13
STM32MP13 is a single Cortex-A7 CPU, without co-processor.
As for STM32MP15x SoC family, STM32MP15x SoCs come with different
features, depending on SoC version. Each peripheral node is created.
Some are left empty for the moment , and will be filled later on.
Yann Gautier [Tue, 12 Jan 2021 14:52:19 +0000 (15:52 +0100)]
feat(stm32mp1): manage HSLV on STM32MP13
On STM32MP13, the high speed mode for pads in low voltage is different
from STM32MP15. Each peripheral supporting the feature has its own
register.
Special care is taken for SDMMC peripherals. The HSLV mode is enabled
only if the max voltage for the pads is lower or equal to 1.8V.
Yann Gautier [Tue, 17 Nov 2020 14:27:58 +0000 (15:27 +0100)]
feat(stm32mp1): update IO compensation on STM32MP13
On STM32MP13, two new SD1 and SD2 IO compensations cells are added,
for SDMMC1 and SDMMC2. They have to be managed the same way as the
main compensation cell.
Yann Gautier [Tue, 18 Jan 2022 09:39:52 +0000 (10:39 +0100)]
feat(stm32mp1): call pmic_voltages_init() in platform init
The nominal voltage for VDDCPU when Cortex-A7 runs at 650MHz is 1.25V
on STM32MP13. VDDCORE should be set at 1.25V as well.
This is necessary, as the PMIC values in its NVMEM are 1.2V.
Yann Gautier [Tue, 18 Jan 2022 14:49:42 +0000 (15:49 +0100)]
feat(st-pmic): add pmic_voltages_init() function
This new function pmic_voltages_init() is used to set the minimum value
for STM32MP13 VDDCPU and VDDCORE regulators. This value is retrieved
from device tree.
Nicolas Le Bayon [Thu, 26 Nov 2020 08:57:09 +0000 (09:57 +0100)]
feat(stm32mp1): update CFG0 OTP for STM32MP13
This field is now declared on the 10 LSB bits on STM32MP13.
Several possible values are specified in the Reference Manual, and
indicate an open or closed device. Other values lead to a system panic.
Change-Id: I697124a21db66a56e7e223d601aa7cf44bb183c4 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Yann Gautier [Thu, 10 Mar 2022 10:33:13 +0000 (11:33 +0100)]
feat(dt-bindings): add bindings for STM32MP13
Add dedicated clock and reset dt-bindings include files. The former
files are renamed with stm32mp15, and the stm32mp1 file just
determine through STM32MP13 or STM32MP15 flag which file to include.
feat(stm32mp1): adaptations for STM32MP13 image header
The header must now include by default at least an extra padding
header, increasing the size of the header to 512 bytes (0x200).
This header will be placed at the end of SRAM3 by BootROM, letting
the whole SYSRAM to TF-A.
The boot context is now placed in SRAM2, hence this memory has to be
mapped in BL2 MMU. This mapping is done for all SRAMs in a 2MB area.
Yann Gautier [Wed, 12 Feb 2020 14:38:34 +0000 (15:38 +0100)]
feat(stm32mp1): add part numbers for STM32MP13
Add the new part numbers and adapt the functions that use them.
There is no package number in OTP as they all share the same GPIO
banks.
This part is then stubbed for STM32MP13.
Yann Gautier [Wed, 12 Feb 2020 08:36:23 +0000 (09:36 +0100)]
feat(stm32mp1): remove unsupported features on STM32MP13
* GPIO: On STM32MP13, there are no banks GPIOJ, GPIOK and GPIOZ.
* STM32MP13 is a single Cortex-A7 CPU: remove reset from MPU1
and reset from MCU traces
* There is no MCU on STM32MP13. Put MCU security management
under STM32MP15 flag.
* The authentication feature is not supported yet on STM32MP13,
put the code under SPM32MP15 flag.
* On STM32MP13, the monotonic counter is managed in ROM code, keep
the monotonic counter update just for STM32MP15.
* SYSCFG: put registers not present on STM32MP13 under STM32MP15
flag, as the code that manages them.
* PMIC: use ldo3 during DDR configuration only for STM32MP15
* Reset UART pins on USB boot is no more required.
Change-Id: Iceba59484a9bb02828fe7e99f3ecafe69c837bc7 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
STM32MP13 is a variant of STM32MP1, with a single Cortex-A7, and no
Cortex-M4.
There is only one DDR port.
SP_min is not supported, only OP-TEE can be used as monitor.
STM32MP13 uses the header v2.0 format for stm32image generation
for BL2.
Nicolas Le Bayon [Mon, 18 Nov 2019 16:13:42 +0000 (17:13 +0100)]
feat(st): update stm32image tool for header v2
The stm32image tool is updated to manage new header v2.0 for BL2
images.
Add new structure for the header v2.0 management.
Adapt to keep compatibility with v1.0.
Add the header version major and minor in the command line
when executing the tool, as well as binary type (0x10 for BL2).
Bipin Ravi [Thu, 24 Feb 2022 05:45:50 +0000 (23:45 -0600)]
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
This patch applies CVE-2022-23960 workarounds for Cortex-A75,
Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements
the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery
hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to
enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3
is implemented for A57/A72 because some revisions are affected by both
CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace
SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details
of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c
In anticipation of Spectre BHB workaround mitigation patches, we
disable the RECLAIM_INIT_CODE for FVP platform. Since the spectre
BHB mitigation workarounds inevitably increase the size of the various
segments due to additional instructions and/or macros, these segments
cannot be fit in the existing memory layout designated for BL31 image.
The issue is specifically seen in complex build configs for FVP
platform. One such config has TBB with Dual CoT and test secure
payload dispatcher(TSPD) enabled. Even a small increase in individual
segment size in order of few bytes might lead to build fails due to
alignment requirements(PAGE_ALIGN to 4KB).
This is needed to workaround the following build failures observed
across multiple build configs:
aarch64-none-elf-ld.bfd: BL31 init has exceeded progbits limit.
aarch64-none-elf-ld.bfd: /work/workspace/workspace/tf-worker_ws_2/trusted_firmware/build/fvp/debug/bl31/bl31.elf section coherent_ram will not fit in region RAM
aarch64-none-elf-ld.bfd: BL31 image has exceeded its limit.
aarch64-none-elf-ld.bfd: region RAM overflowed by 4096 bytes
Pali Rohár [Wed, 16 Mar 2022 11:38:43 +0000 (12:38 +0100)]
docs(a3k): update documentation about DEBUG mode for UART
DEBUG mode can be enabled without any issue for Armada 37xx and also for
other A7K/A8K/CN913x. There is no incompatibility with Xmodem protocol
like it was written before, because Armada 37xx UART images do not print
anything on UART during image transfer and A7K/A8K/CN913x BLE image
automatically turn off debugging output when booting over UART. Looks
like this incorrect information is some relict from the past.
anans [Tue, 15 Mar 2022 08:07:37 +0000 (13:37 +0530)]
fix(ufs): move nutrs assignment to ufs_init
nutrs is set in ufs_enum (used by get_empty_slot), this will not
be assigned if UFS_FLAGS_SKIPINIT is set in flags during init and
might end up crashing read/write commands
Merge changes from topic "revert-14286-uart_segregation-VURJFOWMTM" into integration
* changes:
Revert "feat(sgi): deviate from arm css common uart related defi..."
Revert "feat(sgi): route TF-A logs via secure uart"
Revert "feat(sgi): add page table translation entry for secure uart"
Revert "feat(sgi): deviate from arm css common uart related defi..."
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Revert "feat(sgi): route TF-A logs via secure uart"
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Revert "feat(sgi): add page table translation entry for secure uart"
Revert submission 14286-uart_segregation
Reason for revert: Need to wait for companion patches in CI and UEFI/Linux to be upstreamed.
Reverted Changes:
I8574b31d5:feat(sgi): add page table translation entry for se...
I8896ae05e:feat(sgi): route TF-A logs via secure uart
I39170848e:feat(sgi): deviate from arm css common uart relate...
Rex-BC Chen [Thu, 2 Dec 2021 06:03:44 +0000 (14:03 +0800)]
feat(mt8186): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.
Bipin Ravi [Thu, 3 Feb 2022 05:03:28 +0000 (23:03 -0600)]
refactor(el3-runtime): change Cortex-A76 implementation of CVE-2018-3639
Re-factored the prior implementation of workaround for CVE-2018-3639
using branch and link instruction to save vector space to include the
workaround for CVE-2022-23960.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib3fe949583160429b5de8f0a4a8e623eb91d87d4
Merge changes from topic "uart_segregation" into integration
* changes:
feat(sgi): add page table translation entry for secure uart
feat(sgi): route TF-A logs via secure uart
feat(sgi): deviate from arm css common uart related definitions
fix(brcm): fix the build failure with mbedTLS config
Patch [1] introduces a mechanism to provide the platform
specified mbedTLS config file, but that result in build failure
for Broadcom platform.
This build failure is due to the absence of the mbedTLS configuration
file i.e. brcm_mbedtls_config.h in the TF-A source code repository.
"fatal error: brcm_mbedtls_config.h: No such file or directory"
This problem was resolved by removing the 'brcm_mbedtls_config.h' entry
from the broadcom platform makefile, allowing this platform to use
the default mbedtls_config.h file.
Rohit Mathew [Mon, 13 Dec 2021 15:40:25 +0000 (15:40 +0000)]
feat(sgi): route TF-A logs via secure uart
Route the boot, runtime and crash stage logs via secure UART port
instead of the existing use of non-secure UART. This aligns with the
security state the PE is in when logs are put out. In addition to this,
this allows consolidation of the UART related macros across all the
variants of the Neoverse reference design platforms.
Rohit Mathew [Mon, 13 Dec 2021 13:50:15 +0000 (13:50 +0000)]
feat(sgi): deviate from arm css common uart related definitions
The Neoverse reference design platforms will migrate to use different
set of secure and non-secure UART ports. This implies that the board
specific macros defined in the common Arm platform code will no longer
be usable for Neoverse reference design platforms.
In preparation for migrating to a different set of UART ports, add a
Neoverse reference design platform specific copy of the board
definitions. The value of these definitions will be changed in
subsequent patches.
The previous delegating/undelegating sequence was incorrect as per the
specification DDI0615, "Architecture Reference Manual Supplement, The
Realm Management Extension (RME), for Armv9-A" Sections A1.1.1 and
A1.1.2
Off topic:
- cleaning the gpt_is_gpi_valid and gpt_check_pass_overlap
Change-Id: Idb64d0a2e6204f1708951137062847938ab5e0ac Signed-off-by: Robert Wakim <robert.wakim@arm.com>
Merge changes I713f6e93,Iac4fbf4d,I43d02c77,Iadecd544,Ib31f9c4a, ... into integration
* changes:
build(intel): enable access to on-chip ram in BL31 for N5X
fix(intel): make FPGA memory configurations platform specific
fix(intel): fix ECC Double Bit Error handling
build(intel): define a macro for SIMICS build
build(intel): add N5X as a new Intel platform
build(intel): initial commit for crypto driver
Olivier Deprez [Tue, 25 May 2021 09:56:01 +0000 (11:56 +0200)]
fix(fvp): op-tee sp manifest doesn't map gicd
Following I2d274fa897171807e39b0ce9c8a28824ff424534:
Remove GICD registers S2 mapping from OP-TEE partition when it runs in a
secure partition on top of Hafnium.
The partition is not meant to access the GIC directly but use the
Hafnium provided interfaces.
Michal Simek [Wed, 9 Mar 2022 07:53:20 +0000 (08:53 +0100)]
fix(xilinx): fix coding style violations
Fix coding style violations and alignments:
- Remove additional newlines in headers
- Remove additional newlines in code
- Add newline to separate variable from the code
- Use the same indentation in platform.mk
- Align function parameters
- Use tabs for indentation in kernel-doc format
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I0b12804ff63bc19778e8f21041f9accba5b488b9
Boon Khai Ng [Fri, 21 May 2021 14:56:37 +0000 (22:56 +0800)]
build(intel): enable access to on-chip ram in BL31 for N5X
This adds the ncore ccu access and enable access to the
on-chip ram for N5X device in BL31.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I713f6e93d33b6e91705547477ca32cfba5c8c13d
Sieu Mun Tang [Mon, 28 Feb 2022 07:24:59 +0000 (15:24 +0800)]
fix(intel): make FPGA memory configurations platform specific
Define FPGA_CONFIG_SIZE and FPGA_CONFIG_ADDR in
platform-specific header. This is due to different
allocated sizes between platforms.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iac4fbf4d4940cdf31834a9d4332f9292870dee76
projects / arm-tf.git / log