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3 years agoMerge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration
Manish Pandey [Thu, 28 Apr 2022 16:51:50 +0000 (18:51 +0200)]
Merge changes I80661161,I82c1fa93,I018ccbb9,Ibc23734d,I97406abe, ... into integration

* changes:
  feat(intel): add SMC support for HWMON voltage and temp sensor
  feat(intel): add SMC support for Get USERCODE
  fix(intel): extend SDM command to return the SDM firmware version
  feat(intel): add SMC for enquiring firmware version
  fix(intel): configuration status based on start request
  fix(intel): bit-wise configuration flag handling
  fix(intel): get config status OK status
  fix(intel): use macro as return value
  fix(intel): fix fpga config write return mechanism
  feat(intel): add SiP service for DCMF status
  feat(intel): add RSU 'Max Retry' SiP SMC services
  feat(intel): enable SMC SoC FPGA bridges enable/disable
  feat(intel): add SMC/PSCI services for DCMF version support
  feat(intel): allow to access all register addresses if DEBUG=1
  fix(intel): modify how configuration type is handled
  feat(intel): support SiP SVC version
  feat(intel): enable firewall for OCRAM in BL31
  feat(intel): create source file for firewall configuration
  fix(intel): refactor NOC header

3 years agoMerge "feat(qemu): add support for measured boot" into integration
Manish Pandey [Thu, 28 Apr 2022 15:18:47 +0000 (17:18 +0200)]
Merge "feat(qemu): add support for measured boot" into integration

3 years agofeat(intel): add SMC support for HWMON voltage and temp sensor
Kris Chaplin [Fri, 25 Jun 2021 10:31:52 +0000 (11:31 +0100)]
feat(intel): add SMC support for HWMON voltage and temp sensor

Add support to read temperature and voltage using SMC command

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I806611610043906b720b5096728a5deb5d652b1d

3 years agofeat(intel): add SMC support for Get USERCODE
Sieu Mun Tang [Wed, 27 Apr 2022 10:57:29 +0000 (18:57 +0800)]
feat(intel): add SMC support for Get USERCODE

This patch adds SMC support for enquiring FPGA's User Code.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I82c1fa9390b6f7509b2284d51e199fb8b6a9b1ad

3 years agofix(intel): extend SDM command to return the SDM firmware version
Sieu Mun Tang [Wed, 27 Apr 2022 10:54:10 +0000 (18:54 +0800)]
fix(intel): extend SDM command to return the SDM firmware version

Updates intel_smc_fw_version function to read SDM
firmware version in major/minor ACDS release number.
Update CONFIG_STATUS Response Data [1] bit0-23.

Return INTEL_SIP_SMC_STATUS_ERROR if unexpected
firmware version is being retrieved.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I018ccbb961786a75dc6eb873b0f232e71341e1d2

3 years agofeat(intel): add SMC for enquiring firmware version
Abdul Halim, Muhammad Hadi Asyrafi [Fri, 5 Feb 2021 03:50:58 +0000 (11:50 +0800)]
feat(intel): add SMC for enquiring firmware version

This command allows non-secure world software to enquire the
version of currently running Secure Device Manager (SDM) firmware.

This will be useful in maintaining backward-compatibility as well
as ensuring software cross-compabitility.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibc23734d1135db74423da5e29655f9d32472a3b0

3 years agofix(intel): configuration status based on start request
Abdul Halim, Muhammad Hadi Asyrafi [Tue, 29 Dec 2020 08:49:23 +0000 (16:49 +0800)]
fix(intel): configuration status based on start request

Configuration status command now returns the result based on the last
config start command made to the runtime software. The status type can
be either:
- NO_REQUEST (default)
- RECONFIGURATION
- BITSTREAM_AUTH

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I97406abe09b49b9d9a5b43e62fe09eb23c729bff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
3 years agofix(intel): bit-wise configuration flag handling
Sieu Mun Tang [Thu, 28 Apr 2022 14:40:58 +0000 (22:40 +0800)]
fix(intel): bit-wise configuration flag handling

Change configuration type handling to bit-wise flag. This is to align
with Linux's FPGA Manager definitions and promotes better compatibility.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I5aaf91d3fec538fe3f4fe8395d9adb47ec969434

3 years agofix(intel): get config status OK status
Abdul Halim, Muhammad Hadi Asyrafi [Fri, 20 Nov 2020 03:41:59 +0000 (11:41 +0800)]
fix(intel): get config status OK status

Config status have different OK requirement between MBOX_CONFIG_STATUS
and MBOX_RECONFIG_STATUS request. This patch adds the checking to
differentiate between both command.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I45a4c3de460b031757dbcbd0b3a8055cb0a55aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
3 years agofix(intel): use macro as return value
Abdul Halim, Muhammad Hadi Asyrafi [Fri, 20 Nov 2020 03:06:00 +0000 (11:06 +0800)]
fix(intel): use macro as return value

SMC function should strictly return INTEL_SIP_SMC_STATUS macro. Directly
returning value of variable status might cause confusion in calling
software.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iea17f4feaa5c917e8b995471f3019dba6ea8dcd3
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
3 years agoMerge changes from topic "vendor_makefile_extension" into integration
Manish Pandey [Thu, 28 Apr 2022 14:25:34 +0000 (16:25 +0200)]
Merge changes from topic "vendor_makefile_extension" into integration

* changes:
  feat(plat/mediatek/build_helpers): introduce mtk makefile
  build(makefile): add extra makefile variable for extension

3 years agofix(intel): fix fpga config write return mechanism
Abdul Halim, Muhammad Hadi Asyrafi [Thu, 5 Nov 2020 10:00:03 +0000 (18:00 +0800)]
fix(intel): fix fpga config write return mechanism

This revert commit 279c8015fefcb544eb311b9052f417fc02ab84aa.
The previous change breaks this feature compatibility with Linux driver.
Hence, the fix for the earlier issue is going to be fixed in uboot instead.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I93220243bad65ed53322050d990544c7df4ce66b

3 years agofeat(intel): add SiP service for DCMF status
Sieu Mun Tang [Thu, 28 Apr 2022 14:21:01 +0000 (22:21 +0800)]
feat(intel): add SiP service for DCMF status

This patch adds 2 additional RSU SiP services for Intel SoCFPGA
platforms:
- INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS stores current DCMF status in
  BL31
- INTEL_SIP_SMC_RSU_DCMF_STATUS is calling function for non-secure
  software to retrieve stored DCMF status

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic7a3e6988c71ad4bf66c58a1d669956524dfdf11

3 years agoMerge "docs(build): update GCC to version 11.2-2022.02" into integration
Madhukar Pappireddy [Thu, 28 Apr 2022 14:18:43 +0000 (16:18 +0200)]
Merge "docs(build): update GCC to version 11.2-2022.02" into integration

3 years agoMerge changes from topic "qemu-measured-boot" into integration
Manish Pandey [Thu, 28 Apr 2022 14:17:00 +0000 (16:17 +0200)]
Merge changes from topic "qemu-measured-boot" into integration

* changes:
  fix(arm): fix fvp and juno build with USE_ROMLIB option
  feat(fdt-wrappers): add function to find or add a sudnode

3 years agofeat(intel): add RSU 'Max Retry' SiP SMC services
Chee Hong Ang [Wed, 1 Jul 2020 06:22:25 +0000 (14:22 +0800)]
feat(intel): add RSU 'Max Retry' SiP SMC services

Add SiP SMC services to store/retrieve 'Max Retry' counter
for Remote System Update (RSU).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I17c1f0107ead64e6160954d26407f399003bcbd9

3 years agoMerge "fix(bl2): define RAM_NOLOAD for XIP" into integration
Madhukar Pappireddy [Thu, 28 Apr 2022 14:10:21 +0000 (16:10 +0200)]
Merge "fix(bl2): define RAM_NOLOAD for XIP" into integration

3 years agoMerge changes from topic "ti-k3-system-suspend-base-support" into integration
Madhukar Pappireddy [Thu, 28 Apr 2022 14:05:47 +0000 (16:05 +0200)]
Merge changes from topic "ti-k3-system-suspend-base-support" into integration

* changes:
  feat(ti): allow build config of low power mode support
  feat(ti): increase SEC_SRAM_SIZE to 128k
  feat(ti): add PSCI handlers for system suspend
  feat(ti): add gic save and restore calls
  feat(ti): add enter sleep method

3 years agofeat(qemu): add support for measured boot
Ruchika Gupta [Fri, 8 Apr 2022 07:44:44 +0000 (13:14 +0530)]
feat(qemu): add support for measured boot

Add helper functions to generate event log for qemu
when MEASURED_BOOT=1.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Change-Id: I17a098cb614a3a89fe0fe9577bed6edda8bfd070

3 years agofix(arm): fix fvp and juno build with USE_ROMLIB option
Manish V Badarkhe [Tue, 19 Apr 2022 08:40:15 +0000 (09:40 +0100)]
fix(arm): fix fvp and juno build with USE_ROMLIB option

Change-Id: I8a9b30a952be594435003f0d684e3faad484e8b8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
3 years agofeat(fdt-wrappers): add function to find or add a sudnode
Ruchika Gupta [Fri, 8 Apr 2022 07:46:16 +0000 (13:16 +0530)]
feat(fdt-wrappers): add function to find or add a sudnode

This change adds a new utility function - `fdtw_find_or_add_subnode`
to find a subnode. If the subnode is not present, the function adds
it in the flattened device tree.

Signed-off-by: Ruchika Gupta <ruchika.gupta@linaro.org>
Change-Id: Idf3ceddc57761ac015763d4a8b004877bcad766a

3 years agofeat(intel): enable SMC SoC FPGA bridges enable/disable
Abdul Halim, Muhammad Hadi Asyrafi [Thu, 18 Jun 2020 08:21:29 +0000 (16:21 +0800)]
feat(intel): enable SMC SoC FPGA bridges enable/disable

Enable SoC FPGA bridges enable/disable from non-secure world
through secure monitor calls

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4474abab9731923a61ff0e7eb2c2fa32048001cb
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
3 years agofeat(intel): add SMC/PSCI services for DCMF version support
Chee Hong Ang [Wed, 13 May 2020 03:44:04 +0000 (11:44 +0800)]
feat(intel): add SMC/PSCI services for DCMF version support

Support get/store RSU DCMF version:
INTEL_SIP_SMC_RSU_DCMF_VERSION - Get current DCMF version
INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION - Store current DCMF version

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I85ffbc0efc859736899d4812f040fd7be17c8d8d

3 years agofeat(intel): allow to access all register addresses if DEBUG=1
Siew Chin Lim [Tue, 11 May 2021 13:12:22 +0000 (21:12 +0800)]
feat(intel): allow to access all register addresses if DEBUG=1

Allow to access all register addresses from SMC call if compile the code
with DEBUG=1 for debugging purpose.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Idd31827fb71307efbdbcceeaa05f6cb072842e10

3 years agofix(intel): modify how configuration type is handled
Abdul Halim, Muhammad Hadi Asyrafi [Fri, 29 May 2020 04:13:17 +0000 (12:13 +0800)]
fix(intel): modify how configuration type is handled

This patch creates macros to handle different configuration
types. These changes will help in adding new configuration
types in the future.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I5826a8e5942228a9ed376212f0df43b1605c0199

3 years agofeat(intel): support SiP SVC version
Sieu Mun Tang [Wed, 27 Apr 2022 10:24:06 +0000 (18:24 +0800)]
feat(intel): support SiP SVC version

This command supports to return SiP SVC major and minor version.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ia8bf678b8de0278aeaae748f24bdd05f8c9f9b47

3 years agofeat(intel): enable firewall for OCRAM in BL31
Abdul Halim, Muhammad Hadi Asyrafi [Wed, 5 Aug 2020 14:40:46 +0000 (22:40 +0800)]
feat(intel): enable firewall for OCRAM in BL31

Set OCRAM as secure region and required privileged access in BL31 to
prevent software running in normal world (non-secure) accessing memory
region in OCRAM which may contain sensitive information (e.g. FSBL,
handoff data)

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib6b24efd69f49cd3f9aa4ef2ea9f1af5ce582bd6
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
3 years agofeat(intel): create source file for firewall configuration
Abdul Halim, Muhammad Hadi Asyrafi [Thu, 6 Aug 2020 02:21:54 +0000 (10:21 +0800)]
feat(intel): create source file for firewall configuration

Move codes that previously were part of system_manager driver into
firewall driver which are more appropriate based on their functionalities.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I35e9d792f35ee7491c2f306781417a0c8faae3fd
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
3 years agofix(intel): refactor NOC header
Abdul Halim, Muhammad Hadi Asyrafi [Wed, 5 Aug 2020 14:12:23 +0000 (22:12 +0800)]
fix(intel): refactor NOC header

Refactor NOC header to be shareable across both Stratix 10 and Agilex
platforms. This patch also removes redundant NOC declarations in system
manager header file.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I6348b67a8b54c2ad19327d6b8c25ae37d25e4b4a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
3 years agofeat(plat/mediatek/build_helpers): introduce mtk makefile
Leon Chen [Thu, 24 Mar 2022 02:55:08 +0000 (10:55 +0800)]
feat(plat/mediatek/build_helpers): introduce mtk makefile

In order to modularize software libraries and platform drivers,
we create makefile helpers to treat a folder as a basic compile
unit.

Each module has a build rule (rules.mk) to describe driver and software
library source codes to be built in.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: Ib2113b259dc97937b7295b265509025b43b14077

3 years agobuild(makefile): add extra makefile variable for extension
Leon Chen [Wed, 23 Mar 2022 10:51:48 +0000 (18:51 +0800)]
build(makefile): add extra makefile variable for extension

Introduce EXTRA_LINKERFILE for GCC linker options. GCC linker
can realize multiple linker scripts, and vendors can extend ro or
text sections by inserting sections among the original sections
specified by blx.ld.S.

Vendors can assign compiled object files by assigning MODULE_OBJS
with their own built path.

Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I1bd2e0383a52204723816131da4b7948def4c4e9

3 years agofeat(ti): allow build config of low power mode support
Dave Gerlach [Fri, 11 Feb 2022 19:57:19 +0000 (13:57 -0600)]
feat(ti): allow build config of low power mode support

Not all K3 platforms support low power mode, so to allow these
features to be included for platforms that do in build and
therefore reported in the PSCI caps, define K3_PM_SYSTEM_SUSPEND
flag that can be set during build that will cause appropriate
space and functionality to be included in build for system
suspend support.

Change-Id: I821fbbd5232d91de6c40f63254b855e285d9b3e8
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agofeat(ti): increase SEC_SRAM_SIZE to 128k
Dave Gerlach [Fri, 7 Jan 2022 14:11:10 +0000 (08:11 -0600)]
feat(ti): increase SEC_SRAM_SIZE to 128k

Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agofeat(ti): add PSCI handlers for system suspend
Dave Gerlach [Tue, 30 Nov 2021 21:45:34 +0000 (15:45 -0600)]
feat(ti): add PSCI handlers for system suspend

Add necessary K3 PSCI handlers to enable system suspend to be reported
in the PSCI capabilities when asked during OS boot.

Additionally, have the handlers provide information that all domains
should be off and also have the power domain suspend handler invoke the
TISCI_MSG_ENTER_SLEEP message to enter system suspend.

Change-Id: I351a16167770e9909e8ca525ee0d74fa93331194
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agofeat(ti): add gic save and restore calls
Dave Gerlach [Fri, 7 Jan 2022 14:12:39 +0000 (08:12 -0600)]
feat(ti): add gic save and restore calls

Add functions to save and restore GICv3 redist and dist contexts during
low power mode and then call these during the suspend entry and finish
psci handlers.

Change-Id: I26c2c0f3b7fc925de3b349499fa42d2405441577
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agofeat(ti): add enter sleep method
Dave Gerlach [Tue, 30 Nov 2021 21:35:08 +0000 (15:35 -0600)]
feat(ti): add enter sleep method

This TISCI API must be used to trigger entry into system suspend, and
this is done through the use of TI_SCI_MSG_ENTER_SLEEP. Introduce a
method to send this message.

Change-Id: Id7af5fb2a34623ad69e76764f389ff4d8d259fba
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
3 years agoMerge "docs(zynqmp): update the make command" into integration
Madhukar Pappireddy [Wed, 27 Apr 2022 14:41:21 +0000 (16:41 +0200)]
Merge "docs(zynqmp): update the make command" into integration

3 years agoMerge changes Ibe6fd206,Icdca3de6,I72016620,I57a2787c into integration
Madhukar Pappireddy [Wed, 27 Apr 2022 14:40:38 +0000 (16:40 +0200)]
Merge changes Ibe6fd206,Icdca3de6,I72016620,I57a2787c into integration

* changes:
  fix(versal): fix coverity scan warnings
  feat(versal): get version for ATF related EEMI APIs
  feat(versal): enhance PM_IOCTL EEMI API to support additional arg
  feat(versal): add common interfaces to handle EEMI commands

3 years agoMerge "refactor(twed): improve TWED enablement in EL-3" into integration
Manish Pandey [Wed, 27 Apr 2022 09:01:52 +0000 (11:01 +0200)]
Merge "refactor(twed): improve TWED enablement in EL-3" into integration

3 years agoMerge changes from topic "st_clk_fix" into integration
Manish Pandey [Wed, 27 Apr 2022 08:35:12 +0000 (10:35 +0200)]
Merge changes from topic "st_clk_fix" into integration

* changes:
  fix(st-clock): correct stm32_clk_parse_fdt_by_name
  fix(st-clock): check _clk_stm32_get_parent return

3 years agodocs(zynqmp): update the make command
Venkatesh Yadav Abbarapu [Mon, 11 Apr 2022 03:43:17 +0000 (09:13 +0530)]
docs(zynqmp): update the make command

Update the make command with the RESET_TO_BL31=1 addition.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I46cc81abb539773706348464b3061d20d94522e9

3 years agofix(versal): fix coverity scan warnings
Tanmay Shah [Wed, 23 Mar 2022 19:43:45 +0000 (12:43 -0700)]
fix(versal): fix coverity scan warnings

- Fix memory overrun issue
- include header file to fix Unknown macro warning

Change-Id: Ibe6fd206f44fbc22de746d255ff17c2b2325cd7b
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
3 years agofeat(versal): get version for ATF related EEMI APIs
Ronak Jain [Fri, 4 Feb 2022 08:42:55 +0000 (00:42 -0800)]
feat(versal): get version for ATF related EEMI APIs

The patch does below things.

1. As per current implementation, when Linux send a request to ATF to
 get the version of APIs which are implemented in ATF then ATF wasn't
 returning any version because there is a check for LIBPM module id.
 The ATF is used to return version for the APIs which are implemented
 in the firmware only.

 Hence moved this switch-case before checking module id to get ATF
 version.

 Also, no need to pass Linux request to the firmware for the APIs
 which are implemented in ATF instead return success after updating
 version.

2. As per current implementation, higher 16-bit is used for ATF
 version and lower 16-bit is used for firmware version. Now, removed
 16-bit shift operation and send complete word i.e. 32-bit to Linux
 user as there is no user who checks ATF version.

3. Add bit mask support in the feature check PM EEMI API for QUERY and
 IOCTL ids.

Change-Id: Icdca3de6659f3b673b81a423ed79a3c20b678768
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
3 years agofeat(versal): enhance PM_IOCTL EEMI API to support additional arg
Venkatesh Yadav Abbarapu [Thu, 21 Oct 2021 04:11:53 +0000 (22:11 -0600)]
feat(versal): enhance PM_IOCTL EEMI API to support additional arg

Currently, SMC handler is limited to parsing 5 arguments (1 API ID + 4
32-bit command args). Extend this handling to support one more 32-bit
command argument which is necessary to support new IOCTL IDs for
secure read/write interface.

Note that, this change is completely transparent and does not affect
existing functionality of any of the EEMI APIs.

Change-Id: I72016620eeeaf598f14853512120bfb30bb9a3e9
Signed-off-by: Izhar Ameer Shaikh <izhar.ameer.shaikh@xilinx.com>
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
3 years agofeat(versal): add common interfaces to handle EEMI commands
Tanmay Shah [Mon, 9 Aug 2021 18:00:41 +0000 (11:00 -0700)]
feat(versal): add common interfaces to handle EEMI commands

This change adds common interfaces to handle commands from firmware driver
to power management controller. It removes big chunk of source line of code
that was handling each command separately and doing same repetitive work.

EEMI - Embedded Energy Management Interface is Xilinx proprietary
protocol to allow communication between power management controller
and different processing clusters.

As of now, Each EEMI command has its own implementation in TF-A.
This is redundant. Essentially most EEMI command implementation
in TF-A  does same work. It prepares payload received from kernel, sends
payload to firmware, receives response from firmware and send response
back to kernel.

The same functionality can be achieved if common interface is used among
multiple EEMI commands. This change divides platform management related
SMCCC requests into 4 categories.

1) EEMI commands required for backward compatibility.

Some EEMI commands are still required for backward compatibility
until removed completely or its use is changed to accommodate
common interface

2) EEMI commands that require for PSCI interface and accessed from debugfs

For example EEMI calls related to CPU suspend/resume

3) TF-A specific requests

Functionality such as getting TF-A version and getting callback
data for platform management is handled by this interface

4) Common interface for rest of EEMI commands

This handlers performs payload and firmware response transaction job for
rest of EEMI commands. Also it parses module ID from SMC payload and inserts
in IPI request. If not module ID is found, then default is LIBPM_MODULE_ID.
This helps in making common path in TF-A for all the modules in PLM firmware

Change-Id: I57a2787c7fff9f2e1d1f9003b3daab092632d57e
Signed-off-by: Tanmay Shah <tanmay.shah@xilinx.com>
3 years agoMerge "feat(tc): enable CI-700 PMU for profiling" into integration
Madhukar Pappireddy [Tue, 26 Apr 2022 21:16:53 +0000 (23:16 +0200)]
Merge "feat(tc): enable CI-700 PMU for profiling" into integration

3 years agofeat(tc): enable CI-700 PMU for profiling
Rupinderjit Singh [Tue, 22 Feb 2022 21:50:33 +0000 (21:50 +0000)]
feat(tc): enable CI-700 PMU for profiling

Change-Id: Iaafdfc440b362022e6103eabf3fb2ebed85b6575
Signed-off-by: Rupinderjit Singh <rupinderjit.singh@arm.com>
3 years agoMerge "docs(intel): add Sieu Mun and Benjamin Jit Loon as maintainers" into integration
Joanna Farley [Tue, 26 Apr 2022 10:18:18 +0000 (12:18 +0200)]
Merge "docs(intel): add Sieu Mun and Benjamin Jit Loon as maintainers" into integration

3 years agoMerge changes from topic "sb/mbedtls-2.28" into integration
Sandrine Bailleux [Tue, 26 Apr 2022 05:49:06 +0000 (07:49 +0200)]
Merge changes from topic "sb/mbedtls-2.28" into integration

* changes:
  docs(prerequisites): upgrade to mbed TLS 2.28.0
  build(deps): upgrade to mbed TLS 2.28.0

3 years agoMerge "fix(xilinx): fix mismatching function prototype" into integration
Madhukar Pappireddy [Tue, 26 Apr 2022 02:45:16 +0000 (04:45 +0200)]
Merge "fix(xilinx): fix mismatching function prototype" into integration

3 years agoMerge changes Iccfa7ec6,Ide9a7af4 into integration
Lauren Wehrmeister [Mon, 25 Apr 2022 21:02:07 +0000 (23:02 +0200)]
Merge changes Iccfa7ec6,Ide9a7af4 into integration

* changes:
  feat(intel): add macro to switch between different UART PORT
  feat(intel): add SMC support for ROM Patch SHA384 mailbox

3 years agoMerge "fix(bakery_lock): add __unused for clang" into integration
Lauren Wehrmeister [Mon, 25 Apr 2022 20:08:31 +0000 (22:08 +0200)]
Merge "fix(bakery_lock): add __unused for clang" into integration

3 years agoMerge "fix(ufs): fix cache maintenance issues" into integration
Madhukar Pappireddy [Mon, 25 Apr 2022 18:59:58 +0000 (20:59 +0200)]
Merge "fix(ufs): fix cache maintenance issues" into integration

3 years agoMerge changes from topic "st_fwu_bkp_reg" into integration
Madhukar Pappireddy [Mon, 25 Apr 2022 17:28:33 +0000 (19:28 +0200)]
Merge changes from topic "st_fwu_bkp_reg" into integration

* changes:
  feat(stm32mp1): retry 3 times FWU trial boot
  refactor(stm32mp1): update backup reg for FWU

3 years agodocs(prerequisites): upgrade to mbed TLS 2.28.0
Sandrine Bailleux [Fri, 22 Apr 2022 13:47:31 +0000 (15:47 +0200)]
docs(prerequisites): upgrade to mbed TLS 2.28.0

Upgrade to the latest and greatest 2.x release of Mbed TLS library
(i.e. v2.28.0) to take advantage of their bug fixes.

Note that the Mbed TLS project published version 3.x some time
ago. However, as this is a major release with API breakages, upgrading
to 3.x might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to mbed TLS 3.x after the v2.7
release of TF-A.

Change-Id: I887dfd87893169c7be53b986e6c43338d15949d7
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
3 years agobuild(deps): upgrade to mbed TLS 2.28.0
Sandrine Bailleux [Thu, 21 Apr 2022 08:21:29 +0000 (10:21 +0200)]
build(deps): upgrade to mbed TLS 2.28.0

Upgrade to the latest and greatest 2.x release of Mbed TLS library
(i.e. v2.28.0) to take advantage of their bug fixes.

Note that the Mbed TLS project published version 3.x some time
ago. However, as this is a major release with API breakages, upgrading
to 3.x might require some more involved changes in TF-A, which we are
not ready to do. We shall upgrade to mbed TLS 3.x after the v2.7
release of TF-A.

Actually, the upgrade this time simply boils down to including the new
source code module 'constant_time.c' into the firmware.

To quote mbed TLS v2.28.0 release notes [1]:

  The mbedcrypto library includes a new source code module
  constant_time.c, containing various functions meant to resist timing
  side channel attacks. This module does not have a separate
  configuration option, and functions from this module will be
  included in the build as required.

As a matter of fact, if one is attempting to link TF-A against mbed
TLS v2.28.0 without the present patch, one gets some linker errors
due to missing symbols from this new module.

Apart from this, none of the items listed in mbed TLS release
notes [1] directly affect TF-A. Special note on the following one:

  Fix a bug in mbedtls_gcm_starts() when the bit length of the iv
  exceeds 2^32.

In TF-A, we do use mbedtls_gcm_starts() when the firmware decryption
feature is enabled with AES-GCM as the authenticated decryption
algorithm (DECRYPTION_SUPPORT=aes_gcm). However, the iv_len variable
which gets passed to mbedtls_gcm_starts() is an unsigned int, i.e. a
32-bit value which by definition is always less than 2**32. Therefore,
we are immune to this bug.

With this upgrade, the size of BL1 and BL2 binaries does not appear to
change on a standard sample test build (with trusted boot and measured
boot enabled).

[1] https://github.com/Mbed-TLS/mbedtls/releases/tag/v2.28.0

Change-Id: Icd5dbf527395e9e22c8fd6b77427188bd7237fd6
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
3 years agoMerge "docs(prerequisites): update Arm compilers download link" into integration
Sandrine Bailleux [Mon, 25 Apr 2022 08:05:08 +0000 (10:05 +0200)]
Merge "docs(prerequisites): update Arm compilers download link" into integration

3 years agodocs(prerequisites): update Arm compilers download link
Sandrine Bailleux [Fri, 15 Apr 2022 09:17:40 +0000 (11:17 +0200)]
docs(prerequisites): update Arm compilers download link

Right now, TF-A documentation recommends downloading Arm compilers
from:

  https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads

However, this page is now deprecated, as indicated by the banner at
the top of the page. When navigating to the new recommended page, one
can see the following note, which provides the rationale for the
deprecation:

  GNU Toolchain releases from Arm were published previously as two
  separate releases - one for A-profile and the other for R & M
  profiles (GNU Toolchain for A-profile processors and GNU Arm
  Embedded Toolchain).

  Arm GNU Toolchain releases unifies these two into a single release
  and the previous way of releases therefore have been
  discontinued. However, the previous releases will continue to be
  available for reference.

This patch updates the link to the new recommended place for compiler
downloads.

Change-Id: Iefdea3866a1af806a5db2d2288edbb63c543b8ee
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
3 years agoMerge "docs: fix mailing lists URLs" into integration
Sandrine Bailleux [Mon, 25 Apr 2022 05:58:46 +0000 (07:58 +0200)]
Merge "docs: fix mailing lists URLs" into integration

3 years agodocs(intel): add Sieu Mun and Benjamin Jit Loon as maintainers
Sieu Mun Tang [Sat, 19 Mar 2022 06:21:55 +0000 (14:21 +0800)]
docs(intel): add Sieu Mun and Benjamin Jit Loon as maintainers

Add Sieu Mun Tang and Benjamin Jit Loon Lim as new
Intel SocFPGA platform maintainers and remove the
rest of the Intel SocFPGA platform maintainers.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ieb9a35e278d70a12351aaccab90ddc7be09dc861

3 years agoMerge changes from topic "ffa_el3_spmc" into integration
Olivier Deprez [Fri, 22 Apr 2022 19:09:13 +0000 (21:09 +0200)]
Merge changes from topic "ffa_el3_spmc" into integration

* changes:
  feat(spmc): add support for direct req/resp
  feat(spmc): add support for handling FFA_ERROR ABI
  feat(spmc): add support for FFA_MSG_WAIT
  feat(spmc): add function to determine the return path from the SPMC
  feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3
  feat(spmd): update SPMC init flow to use EL3 implementation
  feat(spmc): add FF-A secure partition manager core
  feat(spmc): prevent read only xlat tables with the EL3 SPMC
  feat(spmc): enable building of the SPMC at EL3
  refactor(spm_mm): reorganize secure partition manager code

3 years agoMerge "fix(stm32mp1): correct dtc version check" into integration
Manish Pandey [Fri, 22 Apr 2022 15:22:59 +0000 (17:22 +0200)]
Merge "fix(stm32mp1): correct dtc version check" into integration

3 years agofix(stm32mp1): correct dtc version check
Yann Gautier [Fri, 22 Apr 2022 11:12:37 +0000 (13:12 +0200)]
fix(stm32mp1): correct dtc version check

Depending on the shell used, the grep command can fail, leading to
a wrong dtc version detection. Correct that by adding quotes.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I329ec929559c94bf1bf99b127662c9d978e067cf

3 years agoMerge "feat(spm): add FFA_RX_ACQUIRE forwarding in SPMD" into integration
Olivier Deprez [Thu, 21 Apr 2022 09:35:42 +0000 (11:35 +0200)]
Merge "feat(spm): add FFA_RX_ACQUIRE forwarding in SPMD" into integration

3 years agodocs: fix mailing lists URLs
Sandrine Bailleux [Thu, 21 Apr 2022 08:17:22 +0000 (10:17 +0200)]
docs: fix mailing lists URLs

With the transition to mailman3, the URLs of TF-A and TF-A Tests
mailing lists have changed. However, we still refer to the old
location, which are now dead links.

Update all relevant links throughout the documentation.

There is one link referring to a specific thread on the TF-A mailing
list in the SPM documentation, for which I had to make a guess as to
what's the equivalent mailman3 URL. The old URL scheme indicates that
the thread dates from February 2020 but beyond that, I could not make
sense of the thread id within the old URL so I picked the most likely
match amongst the 3 emails posted on the subject in this time period.

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Reported-by: Kuohong Wang <kuohong.wang@mediatek.com>
Change-Id: I83f4843afd1dd46f885df225931d8458152dbb58

3 years agofeat(spmc): add support for direct req/resp
Marc Bonnici [Mon, 29 Nov 2021 17:05:57 +0000 (17:05 +0000)]
feat(spmc): add support for direct req/resp

Enable the SPMC to handle FFA_MSG_SEND_DIRECT_REQ and
FFA_MSG_SEND_DIRECT_RESP ABIs.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ia196c7405993f600e4fdbf467397ea3fb035a62a

3 years agofeat(spmc): add support for handling FFA_ERROR ABI
Marc Bonnici [Fri, 10 Dec 2021 09:21:56 +0000 (09:21 +0000)]
feat(spmc): add support for handling FFA_ERROR ABI

This ABI is only valid during SP initialisation to indicate
failure. If this occurs during SP initialisation signal a failure,
otherwise respond with a not supported error code.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I0182a1641c0f6850e82173af333be79b594f2318

3 years agofeat(spmc): add support for FFA_MSG_WAIT
Marc Bonnici [Mon, 29 Nov 2021 17:05:33 +0000 (17:05 +0000)]
feat(spmc): add support for FFA_MSG_WAIT

Handle an incoming call of FFA_MSG_WAIT from the secure world
and update the runtime state of the calling partition accordingly.

This ABI can be called in the following scenarios:
  - Used by an SP to signal it has finished initializing.
  - To resume the normal world after handling a secure interrupt
    that interrupted the normal world.
  - To relinquish control back to the normal world.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I929713a2280e8ec291b5b4e8f6d4b49df337228c

3 years agofeat(spmc): add function to determine the return path from the SPMC
Marc Bonnici [Mon, 29 Nov 2021 17:17:29 +0000 (17:17 +0000)]
feat(spmc): add function to determine the return path from the SPMC

Use knowledge of the target partition ID and source security state
to determine which route should be used to exit the SPMC.

There are 3 exit paths:
1) Return to the normal world via the SPMD, this will take care of
   switching contexts if required.
2) Return to the secure world when the call originated in the normal
   world and therefore switch contexts.
3) Return to the secure world when the call originated in the secure
   world, therefore we can return directly.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I4037f3a8a8519e2c9f1876be92806d2c41d0d154

3 years agofeat(spmd): enable handling of FF-A SMCs with the SPMC at EL3
Marc Bonnici [Mon, 29 Nov 2021 18:02:45 +0000 (18:02 +0000)]
feat(spmd): enable handling of FF-A SMCs with the SPMC at EL3

Any FF-A SMC that arrives from the normal world is handled by the
SPMD before being forwarded to the SPMC. Similarly any SMC
arriving from the secure world will hit the SPMC first and be
forwarded to the SPMD if required, otherwise the SPMC will
respond directly.

This allows for the existing flow of handling FF-A ABI's when
the SPMC resides at a lower EL to be preserved.

In order to facilitate this flow the spmd_smc_forward function
has been split and control is either passed to the SPMC or it is
forwarded as before. To allow this the flags and cookie parameters
must now also be passed into this method as the SPMC must be able to
provide these when calling back into the SPMD handler as appropriate.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I84fee8390023295b9689067e14cd25cba23ca39b

3 years agofeat(spmd): update SPMC init flow to use EL3 implementation
Marc Bonnici [Mon, 29 Nov 2021 17:57:03 +0000 (17:57 +0000)]
feat(spmd): update SPMC init flow to use EL3 implementation

Allow the SPMD to initialise an SPMC implementation at EL3 directly
rather than at a lower EL.
This includes removing the requirement to parse an SPMC manifest to
obtain information about the SPMC implementation, in this case since the
SPMD and SPMC reside in the same EL we can hardcode the required
information directly.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I66d1e1b3ec2d0abbfc28b011a32445ee890a331d

3 years agofeat(spmc): add FF-A secure partition manager core
Marc Bonnici [Wed, 1 Dec 2021 17:57:04 +0000 (17:57 +0000)]
feat(spmc): add FF-A secure partition manager core

This patch introduces the core support for enabling an SPMC in EL3
as per the FF-A spec.

The current implemented functionality is targeted to enable
initialization of the SPMC itself and initial support for
bringing up a single S-EL1 SP.

This includes initialization of the SPMC's internal state,
parsing of an SP's manifest, preparing the cpu contexts and
appropriate system registers for the Secure Partition.

The spmc_smc_handler is the main handler for all incoming SMCs
to the SPMC, FF-A ABI handlers and functionality will
be implemented in subsequent patches.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ib33c240b91e54cbd018a69fec880d02adfbe12b9

3 years agoMerge "fix(errata): workaround for Cortex-X2 erratum 2147715" into integration
Joanna Farley [Tue, 19 Apr 2022 15:07:49 +0000 (17:07 +0200)]
Merge "fix(errata): workaround for Cortex-X2 erratum 2147715" into integration

3 years agoMerge changes from topic "st_nvmem_layout" into integration
Manish Pandey [Tue, 19 Apr 2022 14:11:24 +0000 (16:11 +0200)]
Merge changes from topic "st_nvmem_layout" into integration

* changes:
  refactor(stm32mp1-fdts): remove nvmem_layout node
  refactor(stm32mp1): drop the "st,stm32-nvmem-layout" node
  refactor(st): remove useless includes

3 years agoMerge "refactor(ufs): delete unused variables" into integration
Manish Pandey [Tue, 19 Apr 2022 09:51:12 +0000 (11:51 +0200)]
Merge "refactor(ufs): delete unused variables" into integration

3 years agorefactor(twed): improve TWED enablement in EL-3
Jayanth Dodderi Chidanand [Mon, 28 Mar 2022 14:28:55 +0000 (15:28 +0100)]
refactor(twed): improve TWED enablement in EL-3

The current implementation uses plat_arm API under generic code.
"plat_arm" API is a convention used with Arm common platform layer
and is reserved for that purpose. In addition, the function has a
weak definition which is not encouraged in TF-A.

Henceforth, removing the weak API with a configurable macro "TWED_DELAY"
of numeric data type in generic code and simplifying the implementation.
By default "TWED_DELAY" is defined to zero, and the delay value need to
be explicitly set by the platforms during buildtime.

Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: I25cd6f628e863dc40415ced3a82d0662fdf2d75a

3 years agorefactor(ufs): delete unused variables
Jorge Troncoso [Thu, 14 Apr 2022 21:31:29 +0000 (14:31 -0700)]
refactor(ufs): delete unused variables

The result variable is not being used so it's better to delete it.

Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: Icae614076ce1ba7cdc86267473d59a8bec682f6c

3 years agofeat(spmc): prevent read only xlat tables with the EL3 SPMC
Sayanta Pattanayak [Sat, 6 Mar 2021 06:13:06 +0000 (11:43 +0530)]
feat(spmc): prevent read only xlat tables with the EL3 SPMC

If using the EL3 SPMC ensure that we don't mark the translation
tables as read only. The SPMC requires the ability to map and
unmap a partitions RX/TX buffers at runtime.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ibb78a6a2e3847ce4ec74ce81a9bb61ce34fec24c

3 years agofeat(spmc): enable building of the SPMC at EL3
Marc Bonnici [Wed, 1 Dec 2021 18:00:40 +0000 (18:00 +0000)]
feat(spmc): enable building of the SPMC at EL3

Introduce build flag for enabling the secure partition
manager core, SPMC_AT_EL3. When enabled, the SPMC module
will be included into the BL31 image. By default the
flag is disabled.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5ea1b953e5880a07ffc91c4dea876a375850cf2a

3 years agoMerge "refactor(context mgmt): add cm_prepare_el3_exit_ns function" into integration
Joanna Farley [Tue, 12 Apr 2022 15:44:52 +0000 (17:44 +0200)]
Merge "refactor(context mgmt): add cm_prepare_el3_exit_ns function" into integration

3 years agoMerge "refactor(mpam): remove initialization of EL2 registers when EL2 is used" into...
Joanna Farley [Tue, 12 Apr 2022 15:44:41 +0000 (17:44 +0200)]
Merge "refactor(mpam): remove initialization of EL2 registers when EL2 is used" into integration

3 years agoMerge "refactor(context mgmt): refactor the cm_setup_context function" into integration
Joanna Farley [Tue, 12 Apr 2022 15:44:31 +0000 (17:44 +0200)]
Merge "refactor(context mgmt): refactor the cm_setup_context function" into integration

3 years agoMerge "refactor(context mgmt): remove registers accessible only from secure state...
Joanna Farley [Tue, 12 Apr 2022 15:44:00 +0000 (17:44 +0200)]
Merge "refactor(context mgmt): remove registers accessible only from secure state from EL2 context" into integration

3 years agorefactor(context mgmt): add cm_prepare_el3_exit_ns function
Zelalem Aweke [Mon, 31 Jan 2022 22:59:42 +0000 (16:59 -0600)]
refactor(context mgmt): add cm_prepare_el3_exit_ns function

As part of the RFC:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651,
this patch adds the 'cm_prepare_el3_exit_ns' function. The function is
a wrapper to 'cm_prepare_el3_exit' function for Non-secure state.

When EL2 sysregs context exists (CTX_INCLUDE_EL2_REGS is
enabled) EL1 and EL2 sysreg values are restored from the context
instead of directly updating the registers.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9b071030576bb05500d54090e2a03b3f125d1653

3 years agorefactor(mpam): remove initialization of EL2 registers when EL2 is used
Zelalem Aweke [Wed, 2 Feb 2022 21:29:13 +0000 (15:29 -0600)]
refactor(mpam): remove initialization of EL2 registers when EL2 is used

The patch removes initialization of MPAM EL2 registers when an EL2
software exists. The patch assumes the EL2 software will perform
the necessary initializations of the registers.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I5bed81bc22f417bc3e3cbbcd860a8553cd4307cd

3 years agorefactor(context mgmt): refactor the cm_setup_context function
Zelalem Aweke [Wed, 5 Jan 2022 23:12:24 +0000 (17:12 -0600)]
refactor(context mgmt): refactor the cm_setup_context function

This patch splits the function 'cm_setup_context' into four
functions to make it more readable and easier to maintain.

The function is split into the following functions based on
the security state of the context.

 - setup_context_common - performs common initializations
 - setup_secure_context - performs Secure state specific
  initializations
 - setup_realm_context - performs Realm state specific
 initializations
 - setup_ns_context - performs Non-secure state specific
      initializations

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: Ie14a1c2fc6586087e7aa36537cf9064c80802f8f

3 years agorefactor(context mgmt): remove registers accessible only from secure state from EL2...
Zelalem Aweke [Wed, 3 Nov 2021 18:31:53 +0000 (13:31 -0500)]
refactor(context mgmt): remove registers accessible only from secure state from EL2 context

The following registers are only accessible from secure state,
therefore don't need to be saved/restored during world switch.
 - SDER32_EL2
 - VSTCR_EL2
 - VSTTBR_EL2

This patch removes these registers from EL2 context.

Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I24d08aacb1b6def261c7b37d3e1265bb76adafdc

3 years agoMerge "chore(measured boot): remove unused DTC flags" into integration
Lauren Wehrmeister [Tue, 12 Apr 2022 15:19:01 +0000 (17:19 +0200)]
Merge "chore(measured boot): remove unused DTC flags" into integration

3 years agoMerge "style(plat/arm/corstone1000): resolve checkpatch warnings" into integration
Sandrine Bailleux [Tue, 12 Apr 2022 15:17:14 +0000 (17:17 +0200)]
Merge "style(plat/arm/corstone1000): resolve checkpatch warnings" into integration

3 years agodocs(build): update GCC to version 11.2-2022.02
Daniel Boulby [Mon, 4 Apr 2022 15:38:55 +0000 (16:38 +0100)]
docs(build): update GCC to version 11.2-2022.02

This toolchain provides multiple cross compilers and is publicly
available on developer.arm.com.

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: Ia14de2c7d9034a6f0bc56535e961fffc81bcbf29
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
3 years agofix(errata): workaround for Cortex-X2 erratum 2147715
Bipin Ravi [Tue, 8 Mar 2022 16:37:43 +0000 (10:37 -0600)]
fix(errata): workaround for Cortex-X2 erratum 2147715

Cortex-X2 erratum 2147715 is a Cat B erratum that applies to revision
r2p0 and is fixed in r2p1. The workaround is to set CPUACTLR_EL1[22]=1,
which will cause the CFP instruction to invalidate all branch predictor
resources regardless of context.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I2d81867486d9130f2c36cd4554ca9a8f37254b57

3 years agoMerge "refactor(arm): use MBEDTLS_CONFIG_FILE macro" into integration
Sandrine Bailleux [Mon, 11 Apr 2022 12:33:04 +0000 (14:33 +0200)]
Merge "refactor(arm): use MBEDTLS_CONFIG_FILE macro" into integration

3 years agorefactor(arm): use MBEDTLS_CONFIG_FILE macro
Manish V Badarkhe [Mon, 21 Feb 2022 09:43:49 +0000 (09:43 +0000)]
refactor(arm): use MBEDTLS_CONFIG_FILE macro

Used MBEDTLS_CONFIG_FILE macro for including mbedTLS
configuration.

Signed-off-by: Manish V Badarkhe <manish.badarkhe@arm.com>
Change-Id: I374b59a31df3ab1e69481b2c37a6f7455a106b6e

3 years agoMerge "refactor(corstone700): namespace MHU driver filenames" into integration
Sandrine Bailleux [Mon, 11 Apr 2022 10:47:08 +0000 (12:47 +0200)]
Merge "refactor(corstone700): namespace MHU driver filenames" into integration

3 years agofix(xilinx): fix mismatching function prototype
Venkatesh Yadav Abbarapu [Mon, 11 Apr 2022 03:55:44 +0000 (09:25 +0530)]
fix(xilinx): fix mismatching function prototype

The reported function raises a error when compilers assert the flag
`-Warray-parameter=`, signaling that an array-type argument was promoted
to a pointer-type argument. We observed this behaviour with the gcc 11.2
version.

plat/xilinx/common/pm_service/pm_ipi.c:263:34: error: argument 1 of type 'uint32_t *'
{aka 'unsigned int *'} declared as a pointer [-Werror=array-parameter=]
263 | uint32_t calculate_crc(uint32_t *payload, uint32_t bufsize)
      |                        ~~~~~~~~~~^~~~~~~
In file included from plat/xilinx/common/pm_service/pm_ipi.c:16:
plat/xilinx/common/include/pm_ipi.h:30:33: note: previously declared as an array 'uint32_t[8]'
{aka 'unsigned int[8]'}
   30 | uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize);
      |                        ~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~
cc1.real: all warnings being treated as errors

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I7329f2e76ee0ca5faba71eb50babd20a796fee64

3 years agofix(bakery_lock): add __unused for clang
Okash Khawaja [Fri, 8 Apr 2022 17:06:31 +0000 (18:06 +0100)]
fix(bakery_lock): add __unused for clang

is_lock_acquired() function is only used in assert() statements, so when
compiling without asserts, e.g. with DEBUG=0, the function is unused.
this is okay when compiling with gcc because the function is marked as
inline but that doesn't work for clang. let's mark this as __unused to
avoid -Wunused-function warning-as-error.

Change-Id: I93f808fd15f715a65d1bd4f7592affb7997c4bad
Signed-off-by: Okash Khawaja <okash@google.com>
3 years agorefactor(spm_mm): reorganize secure partition manager code
Marc Bonnici [Sun, 19 Dec 2021 21:37:50 +0000 (21:37 +0000)]
refactor(spm_mm): reorganize secure partition manager code

In preparation for adding the EL3 SPMC configuration as defined in
the FF-A specification, restructure the existing SPM_MM code.

With this restructuring of the code, the 'spm_mm' directory is
renamed as 'spm' and the code inside has been split into two
sub-directories named 'common' and 'spm_mm'. The code in 'spm_mm'
directory contains the code that implements the MM interface.
In subsequent patches, the 'spmc' directory will be introduced
under the 'spm' directory providing the code that implements
the 'FF-A' interface.

Currently the common functionality for S-EL1 partitions is
limited to assembler functions to enter and exit an SP
synchronously.

Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I37739b9b53bc68e151ab5c1c0c6a15b3ee362241

3 years agoMerge changes I573e6478,I52dc3bee,I7e543664 into integration
Manish Pandey [Fri, 8 Apr 2022 12:42:45 +0000 (14:42 +0200)]
Merge changes I573e6478,I52dc3bee,I7e543664 into integration

* changes:
  feat(gic600ae_fmu): enable all GICD, PPI, ITS SMs
  feat(gic600ae_fmu): disable SMID for unavailable blocks
  feat(gic600ae_fmu): introduce support for RAS error handling

3 years agochore(measured boot): remove unused DTC flags
Sandrine Bailleux [Fri, 8 Apr 2022 08:25:41 +0000 (10:25 +0200)]
chore(measured boot): remove unused DTC flags

We no longer need to pass special flags to the device tree compiler
for measured boot. These are a left over from the days where we used
to pass BL2 measurement to BL2 image via TB_FW configuration file.

This should have been removed as part of commit eab78e9ba4e36da27
("refactor(measured_boot): remove passing of BL2 hash via device
tree") but was missed at the time.

Change-Id: Iced7e60af7ca660c342c0fc3a33b51865d67f04d
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
3 years agoMerge "build(changelog): add new scope for TI platform" into integration
Manish Pandey [Thu, 7 Apr 2022 15:44:31 +0000 (17:44 +0200)]
Merge "build(changelog): add new scope for TI platform" into integration