Harrison Mutai [Mon, 3 Oct 2022 11:48:35 +0000 (12:48 +0100)]
feat(cpu): add library support for Hunter ELP
Add basic CPU library code to support the Hunter ELP CPU in TF-A.
Hunter-ELP adds v9.2 architecture support and is derived from
Makalu-ELP. As such, the library code is adapted from the
Makalu-ELP support library.
Change-Id: I7e93b9af6b1f0bc4d08c3cf5caf071d2cbdbc89f Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
fix(ras): trap "RAS error record" accesses only for NS
RAS_TRAP_LOWER_EL_ERR_ACCESS was used to prevent access to RAS error
record registers (RAS ERR* & RAS ERX*) from lower EL's in any security
state. To give more fine grain control per world basis re-purpose this
macro to RAS_TRAP_NS_ERR_REC_ACCESS, which will enable the trap only
if Error record registers are accessed from NS.
This will also help in future scenarios when RAS handling(in Firmware
first handling paradigm)can be offloaded to a secure partition.
This is first patch in series to refactor RAS framework in TF-A.
Return values contained in 'smc_result' structure
are shifted down by one register:
X1 written by RMM is returned to NS in X0 and
X5 is returned in X4.
Raef Coles [Wed, 15 Jun 2022 13:37:22 +0000 (14:37 +0100)]
feat(rss): add new comms protocols
The current comms protocol (where arguments and return data is embedded
into the MHU message) is now protocol v0. Protocol v1 embeds pointers
into the message, and has the RSS retrieve the data via DMA.
Change-Id: I08d7f09c4eaea673769fde9eee194447a99f1b78 Signed-off-by: Raef Coles <raef.coles@arm.com>
feat(ls1043ardb): update ddr configure for ls1043ardb-pd
DDR4 Chip is EOL during redesign of ls1043ardb pd version. The replacement from MT is MT40A1G8SA-062E:R.
New ddr configure is compatible with both pd and old version of ls1043ardb.
This fix solves problems with using PRI*PTR on aarch64 like so:
error: format '%x' expects argument of type 'unsigned int', but
argument 3 has type 'uintptr_t' {aka 'long unsigned int'}
Change-Id: I135d3e5cea5459f138b20331b5e9472e2e9e566c Signed-off-by: K <kayo@illumium.org>
feat(sgi): remove override for `ARM_BL31_IN_DRAM` build-option
RD-N2* variants of Neoverse reference design platforms could be
configured to boot from SRAM or DRAM. Having ARM_BL31_IN_DRAM set to 1
within the common makefile would deter these platforms from having this
flexibility. Remove the default override configuration for
`ARM_BL31_IN_DRAM`.
feat(sgi): configure SRAM and BL31 size for sgi platform
Update SRAM size for Neoverse reference design platforms from 256KB to
512KB. This is required to place and execute BL31 image from the
on-chip SRAM. Additionally, revise BL31 image size to accommodate
larger BL31 images of multi-chip platforms.
Merge changes from topic "mediatek upstream" into integration
* changes:
refactor(mt8188): move platform_def.h to mt8188/include
feat(mt8188): add MCUSYS support
feat(mt8188): add armv8.2 support
feat(mt8188): add DFD control in SiP service
feat(mt8188): add EMI MPU basic drivers
feat(mt8188): add DCM driver
feat(mt8188): add reset and poweroff functions
feat(mediatek): add more flexibility of mtk_pm.c
feat(mediatek): add more options for build helper
feat(mt8188): add LPM driver support
feat(mt8188): apply ERRATA for CA-78
fix(mediatek): remove unused cold_boot.[c|h]
fix(mediatek): wrap cold_boot.h with MTK_SIP_KERNEL_BOOT_ENABLE
feat(mt8186): add EMI MPU support for SCP and DSP
Fengquan Chen [Wed, 17 Aug 2022 02:42:15 +0000 (10:42 +0800)]
feat(mt8188): add DFD control in SiP service
DFD (Design for Debug) is a debugging tool, which scans flip-flops and
dumps to internal RAM on the WDT reset. After system reboots, those
values could be showed for debugging.
- Removing platform dependencies from libc modules.
- Replacing panicking with actual error handling.
- Debug macros are included indirectly from assert.h. Removing
"platform_def.h" from assert.h and adding "common/debug.h"
where the macros are used.
- Removing hack for fixing PLAT_LOG_LEVEL_ASSERT to 40.
Instead removing assert with expression, as this
does not provide additional information.
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC
Fix the "#if defined(FOO)" usage introduced by commit 7c2fe62f1
("fix(bl31): allow use of EHF with S-EL2 SPMC") since the defines are
always passed as -DFOO=0 or as -DFOO=1. The "#if defined(FOO)" will now
always be true which is wrong.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Change-Id: I84fb144debc9899727a1fc021acdd59b4a6f0171
feat(versal-net): add support for platform management
Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149
CAAM provides serial output during initialization, but the serial init
occurs after CAAM. This leads to serial output produced by CAAM init
function to be omitted and not displayed.
Change the order of initialization and call CAAM init after Serial. This
has no impact as Serial does not require CAAM to be initialized upfront.
Fixes: 2502709f60de ("plat: imx8m: Add caam module init on imx8m") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I09c0a5474a1babfb0b53c4455891689ec08b5bdb
Michal Simek [Wed, 31 Aug 2022 14:45:14 +0000 (16:45 +0200)]
feat(versal-net): add support for Xilinx Versal NET platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
Serial output is missing the EOL marker, which makes the output garbled.
Add EOL to the output, which adds a newline and makes log output
consistent.
Fixes: 77850c96f23b ("feat(plat/imx8m): do not release JR0 to NS if HAB is using it") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Franck LENORMAND <franck.lenormand@nxp.com> Cc: Jacky Bai <ping.bai@nxp.com>
Change-Id: I58b67f441016122bc9361d7224d310522917eff0
Merge changes from topic "RDN2_WARM_REBOOT_WITH_SGI" into integration
* changes:
feat(sgi): enable css implementation of warm reset
feat(scmi): send powerdown request to online secondary cpus
feat(plat/arm/css): add interrupt handler for reboot request
refactor(psci): move psci_do_pwrdown_sequence() out of private header
feat(plat/arm/css): add per-cpu power down support for warm reset
feat(scmi): set warm reboot entry point
fix(gicv3): update the affinity mask to 8 bit
ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.
feat(scmi): send powerdown request to online secondary cpus
To initiate a reset or reboot, the nonsecure OS invokes the PSCI
SYSTEM_RESET function from any one core. As per the PSCI specification,
it is the responsibility of firmware to implement the system view of
the reset or reboot operation. For the platforms supported by CSS,
trigger the reset/reboot operation by sending an SGI to rest all CPUs
which are online. The CPUs respond to this interrupt by initiating its
powerdown sequence.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
feat(plat/arm/css): add interrupt handler for reboot request
Add platform specific interrupt handler for handling the reboot of
all CPU's. On shutdown/reboot, only one CPU invoke PSCI and enter into
trusted firmware. The CPU which entered trusted firmware signals the
rest of the cores which are online using SGI to initiate power down
sequence. On receiving the SGI, the handler will power down the
GIC redistributor interface of the respective core, configure the power
control register and power down the CPU by executing wfi.
In addition to these changes, fix coding style issues that are not
directly related to the code being introduced in this patch.
refactor(psci): move psci_do_pwrdown_sequence() out of private header
Move the psci_do_pwrdown_sequence() function declaration from PSCI
private header to common header. The psci_do_pwrdown_sequence is
required to support warm reset, where each CPU need to execute the
powerdown sequence.
feat(plat/arm/css): add per-cpu power down support for warm reset
Add a new function to setup a SGI interrupt that will be used to trigger
a request for per-cpu power down when executing the PSCI SYSTEM_RESET
request. This will be used on CSS platform that require all the CPUs to
execute the CPU specific power down sequence to complete a warm reboot
sequence in which only the CPUs are power cycled.
Pranav Madhu [Sat, 11 Dec 2021 16:53:25 +0000 (22:23 +0530)]
feat(scmi): set warm reboot entry point
Before issuing the system power down command, set the trusted mailbox
to 0. This will ensure that in the case of a warm/cold reset, the
primary CPU executes from the cold boot sequence, clearing any stale
jump address at this location.
The script 'sp_mk_generator.py' was reworked in [1]. There was a
reference the variable 'data' left. This variable 'data' used to refer
to the json data of a the sp layout file.
This patch fixed the reference with the proper variable according to the
rework [1].
ICC_SRE_EL2 has only 4 bits, while others are RES0. The library programs
all four of them already, so there is no need to read the previous
settings from the actual register.
This patch removes the explicit register read as a result.
Merge changes from topic "xilinx-misc-changes" into integration
* changes:
chore(zynqmp): fix comment style in zynqmp_def.h
chore(versal): add missing dot at the end of sentence
fix(zynqmp): remove additional 0x in %p print
fix(versal): fix Misra-C violations in bl31_setup and pm_svc_main
Rajan Vaja [Wed, 31 Aug 2022 10:54:34 +0000 (12:54 +0200)]
fix(xilinx): update define for ZynqMP specific functions
Instead of exclude code for Versal, define only for ZynqMP.
For new platforms this code should be excluded so instead of
excluding for all platform, define only for ZynqMP.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I45798dadc0f374c5794f517f7d0158675a75caa9
Rajan Vaja [Wed, 31 Aug 2022 10:54:40 +0000 (12:54 +0200)]
fix(xilinx): remove unnecessary header include
Platform specific IPI header inclusion is not required
in common IPI source file. So remove inclusion of the same.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: I6686757f00370c6ec42b5ee2c44ea5cd13da70c0
Rajan Vaja [Wed, 31 Aug 2022 10:54:38 +0000 (12:54 +0200)]
fix(xilinx): include missing header
pm_ipi.h needs some definitions from stddef.h so include it.
Currently it is working because required file is included
indirectly due to other includes.
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Ic4a6c469c3152e21eaeb365ba96f3a29f14593bf
projects / arm-tf.git / log