Manish Pandey [Fri, 28 Feb 2020 16:52:55 +0000 (16:52 +0000)]
Merge changes I75f6d135,I4add470e,I0ecd3a2b,I67a63d73 into integration
* changes:
board/rddaniel: intialize tzc400 controllers
plat/arm/tzc: add support to configure multiple tzc400
plat/arm: allow boards to specify second DRAM Base address
plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS
It is needed to make it appear in the table of contents. Right now,
all Amlogic documentation pages appear under the "Platform ports"
section, except the AXG one.
Imre Kis [Tue, 17 Dec 2019 17:06:26 +0000 (18:06 +0100)]
Modify multithreaded dts file of DynamIQ FVPs
The dts file now contains a CPU map that precisely describes the
topology including thread nodes. The map was also extended to have 16
PEs to be able to test multithreaded FVPs with 8 cores in the same
cluster.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: If39559b05d20bfd68d0ecf830ddcbc5233b288a0
Masahiro Yamada [Mon, 3 Feb 2020 10:46:40 +0000 (19:46 +0900)]
uniphier: prepare uniphier_soc_info() for next SoC
The revision register address will be changed in the next SoC.
The LSI revision is needed in order to know where the revision
register is located, but you need to read out the revision
register for that. This is impossible.
We need to know the revision register address by other means.
Use BL_CODE_BASE, where the base address of the TF image that is
currently running. If it is bigger than 0x80000000 (i.e. the DRAM
base is 0x80000000), we assume it is a legacy SoC.
Mark Dykes [Tue, 25 Feb 2020 23:39:33 +0000 (23:39 +0000)]
Merge changes from topic "console_t_cleanup" into integration
* changes:
marvell: Consolidate console register calls
uniphier: Use generic console_t data structure
spe: Use generic console_t data structure
LS 16550: Use generic console_t data structure
stm32: Use generic console_t data structure
rcar: Use generic console_t data structure
a3700: Use generic console_t data structure
16550: Use generic console_t data structure
imx: Use generic console_t data structure
Alexei Fedorov [Mon, 24 Feb 2020 10:39:31 +0000 (10:39 +0000)]
FVP: Fix incorrect GIC mapping
This patch fixes incorrect setting for DEVICE1_SIZE
for FVP platforms with more than 8 PEs.
The current value of 0x200000 supports only 8 PEs
and causes exception for FVP platforms with the greater
number of PEs, e.g. FVP_Base_Cortex_A65AEx8 with 16 PEs
in one cluster.
Andre Przywara [Sat, 25 Jan 2020 23:55:08 +0000 (23:55 +0000)]
marvell: Consolidate console register calls
Now that different UARTs share the same console_t struct, we can
simplify the console selection for the Marvell platforms:
We share the same console_t pointers, just change the name of the
console register functions, depending on the selected platform.
Change-Id: I6fe3e49fd7f208a9b3372c5deef43236a12867bc Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 01:07:19 +0000 (01:07 +0000)]
coreboot: Use generic base address
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location for the coreboot memory console.
This removes the base member from the coreboot specific data structure,
but keeps the struct console_cbmc_t and its size member.
Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
pl011: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I7a23327394d142af4b293ea7ccd90b843c54587c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
meson: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I07a07677153d3671ced776671e4f107824d3df16 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:54:38 +0000 (00:54 +0000)]
console: Integrate UART base address in generic console_t
*All* UART drivers in TF-A are storing their base address as a uintptr_t
pointer in the first location of the UART specific driver data.
Since the base address is a pretty natural and generic data item, we
should integrate this into the generic console_t structure.
That will not only allow to remove a lot of seemingly UART specific data
structures, but also enables to simplify runtime choices between different
UARTs, since they can share the same pointer.
This patch just adds the new member, the existing data structures will
be handled on a per-UART base in follow-up patches.
Change-Id: I59ce49471ccc8f3b870f2cfd8a72ebfd0cb14d12 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
uniphier: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: Ia9d996bb45ff3a7f1b240f12fd75805b48a048e9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
skeletton: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I347849424782333149e5912a25cc0ab9d277a201 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
spe: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I75dbfafb67849833b3f7b5047e237651e3f553cd Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
cdns: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I9f8b55414ab7965e431e3e86d182eabd511f32a4 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
LS 16550: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: Ifd6aff1064ba1c3c029cdd8a83f715f7a9976db5 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
stm32: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
rcar: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I836e26ff1771abf21fd460d0ee40e90a452e9b43 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
a3700: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I89c3ab2ed85ab941d8b38ced48474feb4aaa8b7e Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
16550: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 25 Jan 2020 00:58:35 +0000 (00:58 +0000)]
imx: Use generic console_t data structure
Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.
Change-Id: I058f793e4024fa7291e432f5be374a77faf16f36 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This patch comes as fixes for 'intel: Fix Coverity Scan Defects' patch.
Revert changing argument type from uint32_t to uint64_t to fix
incompatible cast issue. Fix said bug by using intermediate uint32_t
array as a more appropriate solution.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I344cdabd432cf0a0389b225c934b35d12f4c631d
This patch introduces a build flag which allows the xlat tables
to be mapped in a read-only region within BL31 memory. It makes it
much harder for someone who has acquired the ability to write to
arbitrary secure memory addresses to gain control of the
translation tables.
The memory attributes of the descriptors describing the tables
themselves are changed to read-only secure data. This change
happens at the end of BL31 runtime setup. Until this point, the
tables have read-write permissions. This gives a window of
opportunity for changes to be made to the tables with the MMU on
(e.g. reclaiming init code). No changes can be made to the tables
with the MMU turned on from this point onwards. This change is also
enabled for sp_min and tspd.
To make all this possible, the base table was moved to .rodata. The
penalty we pay is that now .rodata must be aligned to the size of
the base table (512B alignment). Still, this is better than putting
the base table with the higher level tables in the xlat_table
section, as that would cost us a full 4KB page.
Changing the tables from read-write to read-only cannot be done with
the MMU on, as the break-before-make sequence would invalidate the
descriptor which resolves the level 3 page table where that very
descriptor is located. This would make the translation required for
writing the changes impossible, generating an MMU fault.
Julius Werner [Mon, 12 Mar 2018 20:26:49 +0000 (13:26 -0700)]
mt8173: Add support for new watchdog SMC
This patch adds support for a new SMC that can be used to control the
watchdog. This allows for a cleaner separation of responsibilities where
all watchdog operations have to go through Trusted Firmware and we could
no longer have kernel and firmware poking concurrently at the same
register block.
Signed-off-by: Julius Werner <jwerner@chromium.org> Signed-off-by: Evan Benn <evanbenn@chromium.org>
Change-Id: I4844a3559d5c956a53a74a61dd5bc2956f0cce7b
Manish Pandey [Tue, 14 Jan 2020 11:52:05 +0000 (11:52 +0000)]
SPMD: generate and add Secure Partition blobs into FIP
Till now TF-A allows limited number of external images to be made part
of FIP. With SPM coming along, there may exist multiple SP packages
which need to be inserted into FIP. To achieve this we need a more
scalable approach to feed SP packages to FIP.
This patch introduces changes in build system to generate and add SP
packages into FIP based on information provided by platform.
Platform provides information in form of JSON which contains layout
description of available Secure Partitions.
JSON parser script is invoked by build system early on and generates
a makefile which updates FIP, SPTOOL and FDT arguments which will be
used by build system later on for final packaging.
"SP_LAYOUT_FILE" passed as a build argument and can be outside of TF-A
tree. This option will be used only when SPD=spmd.
For each SP, generated makefile will have following entries
- FDT_SOURCES += sp1.dts
- SPTOOL_ARGS += -i sp1.img:sp1.dtb -o sp1.pkg
- FIP_ARGS += --blob uuid=XXXX-XXX...,file=SP1.pkg
Varun Wadekar [Wed, 20 Jun 2018 00:07:08 +0000 (17:07 -0700)]
Tegra: spe: uninit console on a timeout
There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmware to respond indefinitely.
The console driver must detect such scenarios and uninit the
interface as a result.
This patch adds a timeout to the interaction with the SPE
firmware and uninits the interface if it times out.
Varun Wadekar [Tue, 26 Jun 2018 23:07:50 +0000 (16:07 -0700)]
Tegra: handler to check support for System Suspend
Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".
This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".
Original change by: kalyani chidambaram <kalyanic@nvidia.com>
Varun Wadekar [Wed, 20 Jun 2018 23:12:50 +0000 (16:12 -0700)]
Tegra: bpmp_ipc: improve cyclomatic complexity
Code complexity is a good indication of maintainability versus
testability of a piece of software.
ISO26262 introduces the following thresholds:
complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted
Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.
This patch removes redundant conditionals from 'ipc_send_req_atomic'
handler to reduce the McCabe Cyclomatic Complexity for this function
Varun Wadekar [Wed, 20 Jun 2018 21:30:59 +0000 (14:30 -0700)]
Tegra: platform handler to relocate BL32 image
This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.
Varun Wadekar [Wed, 20 Jun 2018 20:43:43 +0000 (13:43 -0700)]
Tegra: common: improve cyclomatic complexity
Code complexity is a good indication of maintainability versus
testability of a piece of software.
ISO26262 introduces the following thresholds:
complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted
Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.
This patch removes redundant conditionals from 'bl31_early_platform_setup'
handler to reduce the McCabe Cyclomatic Complexity for this function.
This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.
The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.
Varun Wadekar [Mon, 18 Jun 2018 23:15:51 +0000 (16:15 -0700)]
Tegra: delay_timer: support for physical secure timer
This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.
The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.
This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.
Tegra194: memctrl: lock mc stream id security config
This patch locks most of the stream id security config registers as
per HW guidance.
This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.
Tegra210: resume PMC hardware block for all platforms
The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause problems for devices that do not support this
firmware.
This patch fixes this logic and resumes the PMC block even if
the sc7entry-fw is not present on the device.
Varun Wadekar [Wed, 13 Jun 2018 21:54:01 +0000 (14:54 -0700)]
Tegra: macro for legacy WDT FIQ handling
This patch adds the macro to enable legacy FIQ handling to the common
Tegra makefile. The default value of this macro is '0'. Platforms that
need this support should enable it from their makefiles.
This patch also helps fix violation of Rule 20.9.
Rule 20.9 "All identifiers used in the controlling expression of #if
of #elif preprocessing directives shall be #define'd before
evaluation"
The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable
non-cacheable streaming enhancement. Platforms can set this bit only
if their memory system meets the requirement that cache line fill
requests from the Cortex-A57 processor are atomic.
This patch adds support to enable higher performance non-cacheable load
forwarding for such platforms. Platforms must enable this support by
setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their
makefiles. This flag is disabled by default.
Suyash Pathak [Wed, 12 Feb 2020 04:38:55 +0000 (10:08 +0530)]
board/rddaniel: intialize tzc400 controllers
A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
accordingly.
Suyash Pathak [Tue, 4 Feb 2020 08:25:20 +0000 (13:55 +0530)]
plat/arm/tzc: add support to configure multiple tzc400
For platforms that have two or more TZC400 controllers instantiated,
allow the TZC400 driver to be usable with all those instances.
This is achieved by allowing 'arm_tzc400_setup' function to accept
the base address of the TZC400 controller.
Suyash Pathak [Wed, 12 Feb 2020 05:06:20 +0000 (10:36 +0530)]
plat/arm: allow boards to specify second DRAM Base address
The base address for second DRAM varies across different platforms.
So allow platforms to define second DRAM by moving Juno/SGM-775 specific
definition of second DRAM base address to Juno/SGM-775 board definition
respectively, SGI/RD specific definition of DRAM 2 base address to SGI
board definition.
Suyash Pathak [Thu, 6 Feb 2020 06:21:54 +0000 (11:51 +0530)]
plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS
A TZC400 can have upto 4 filters and the number of filters instantiated
within a TZC400 is platform dependent. So allow platforms to define the
value of PLAT_ARM_TZC_FILTERS by moving the existing Juno specific
definition of PLAT_ARM_TZC_FILTERS to Juno board definitions.
board/rdn1edge: use CREATE_SEQ helper macro to compare chip count
Use CREATE_SEQ helper macro to create sequence of valid chip counts
instead of manually creating the sequence. This allows a scalable
approach to increase the valid chip count sequence in the future.
Add `CREATE_SEQ` function to generate sequence of numbers starting from
1 to allow easy comparison of a user defined macro with non-zero
positive numbers.
Rui Silva [Wed, 9 Oct 2019 11:54:30 +0000 (12:54 +0100)]
corstone700: fdts: using DDR memory and XIP rootfs
This patch allows to use DDR address in memory node because on FPGA we
typically use DDR instead of shared RAM.
This patch also modifies the kernel arguments to allow the rootfs to be
mounted from a direct mapping of the QSPI NOR flash using the physmap
driver in the kernel. This allows to support CRAMFS XIP.
Zelalem [Wed, 12 Feb 2020 16:37:03 +0000 (10:37 -0600)]
coverity: fix MISRA violations
Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
underscore, shall not be declared
- Type mismatch in BL1 SMC handlers and tspd_main.c
Mark Dykes [Tue, 18 Feb 2020 16:24:33 +0000 (16:24 +0000)]
Merge changes I4e95678f,Ia7c28704,I1bb04bb4,I93d96dca,I50aef5dd into integration
* changes:
Fix boot failures on some builds linked with ld.lld.
trusty: generic-arm64-smcall: Support gicr address
trusty: Allow gic base to be specified with GICD_BASE
trusty: Allow getting trusty memsize from BL32_MEM_SIZE instead of TSP_SEC_MEM_SIZE
Fix clang build if CC is not in the path.
projects / arm-tf.git / log