Merge changes from topic "tegra194-spmd" into integration
* changes:
Tegra194: introduce support for `SPD=spmd`
Tegra: introduce backend support to compile libfdt
Tegra: disable signed comparison
plat: common: include "bl_common.h" from plat_spmd_manifest.c
plat: common: include "bl_common.h" from plat_spmd_manifest.c
This patch includes the bl_common.h from plat_spmd_manifest.c to
fix the following compilation errors
<snip>
plat/common/plat_spmd_manifest.c: In function 'plat_spm_core_manifest_load':
plat/common/plat_spmd_manifest.c:130:18: error: implicit declaration of function 'page_align' [-Werror=implicit-function-declaration]
130 | pm_base_align = page_align(pm_base, UP);
| ^~~~~~~~~~
plat/common/plat_spmd_manifest.c:130:38: error: 'UP' undeclared (first use in this function); did you mean 'UL'?
130 | pm_base_align = page_align(pm_base, UP);
| ^~
| UL
plat/common/plat_spmd_manifest.c:130:38: note: each undeclared identifier is reported only once for each function it appears in
plat/common/plat_spmd_manifest.c:146:38: error: 'DOWN' undeclared (first use in this function)
146 | pm_base_align = page_align(pm_base, DOWN);
| ^~~~
cc1: all warnings being treated as errors
<snip>
The SMMU configuration can get corrupted or updated by
external clients during boot without our knowledge.
This patch introduces a "verify" function for the SMMU
driver, to check that the boot configuration settings are
intact. Usually, this function should be called at the
end of the boot cycle.
This function only calls panic() on silicon platforms.
Change-Id: I2ab45a7f228781e71c73ba1f4ffc49353effe146 Signed-off-by: George Bauernschmidt <georgeb@nvidia.com>
Varun Wadekar [Thu, 22 Aug 2019 18:52:36 +0000 (11:52 -0700)]
Tegra: TZDRAM setup from soc specific early_boot handlers
TZDRAM setup is not required for all Tegra SoCs. The previous bootloader
can enable the TZDRAM fence due to architectural improvements in the
newer chips.
This patch moves the TZDRAM setup to early_boot handlers for SoCs to
handle this scenario.
Varun Wadekar [Fri, 4 Oct 2019 18:40:56 +0000 (11:40 -0700)]
Tegra: print GICC registers conditionally
The GICC interface exists only on the interrupt controllers following
the GICv2 specification.
This patch prints the GICC register contents from the platform's macro,
plat_crash_print_regs' only when TEGRA_GICC_BASE is defined. This
allows platforms using future versions of the GIC specification to
still use this macro.
SPE no longer requires the flush bit to be set to start transmitting
characters over the physical uart. Therefore, the flush bit is no
longer required when calling console_core_putc. However, flushing the
console still requires the flush bit.
This patch removes the flush bit from the mailbox messages in
console_core_putc to improve ACK latency.
Original change by: Mustafa Bilgen <mbilgen@nvidia.com>
tools: Get the tool's binary name from the main makefile
Currently, the tool's makefile override the tool's binary name
which is already been defined in the main makefile.
Hence fix is provided so that the tool's makefile get the tool's
binary name from the main makefile instead of overriding it.
Change-Id: I8af2bd391a96bba2dbcddef711338a94ebf5f038 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Mark Dykes [Wed, 19 Aug 2020 19:11:33 +0000 (19:11 +0000)]
Revert "libc/memset: Implement function in assembler"
This reverts commit e7d344de01ad11b856233634717aafe9312697e4.
This reverts the patch https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5313 due to a timing issue with the merge. The merge occurred at the same time as the additional comments and thusly were were not seen until the merge was done. This reverts the change and additional patches from Alexei will follow to address the concerns expressed in the orignal patch.
Olivier Deprez [Fri, 21 Aug 2020 14:18:57 +0000 (14:18 +0000)]
Merge changes from topic "spm-secondary-cores" into integration
* changes:
SPMC: embed secondary core ep info into to SPMC context
SPMC: manifest changes to support multicore boot
SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
SPMD: handle SPMC message to register secondary core entry point
SPMD: introduce SPMC to SPMD messages
SPMD: register the SPD PM hooks
SPMD: add generic SPD PM handlers
SPMD: enhance SPMC internal boot states
SPMD: entry point info get helper
Olivier Deprez [Mon, 23 Mar 2020 08:53:06 +0000 (09:53 +0100)]
SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
Define SPMD PM hooks for warm boot and off events. svc_on_finish handler
enters the SPMC at the entry point defined by the secondary EP register
service. The svc_off handler notifies the SPMC that a physical core is
being turned off through a notification message.
SPMD: handle SPMC message to register secondary core entry point
Upon booting, the SPMC running on the primary core shall register the
secondary core entry points to which a given secondary core being woken
up shall jump to into the SPMC . The current implementation assumes the
SPMC calls a registering service implemented in the SPMD for each core
identified by its MPIDR. This can typically happen in a simple loop
implemented in the early SPMC initialization routines by passing each
core identifier associated with an entry point address and context
information.
This service is implemented on top of a more generic SPMC<=>SPMD
interface using direct request/response message passing as defined by
the FF-A specification.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: I1f70163b6b5cee0880bd2004e1fec41e3780ba35
Olivier Deprez [Mon, 28 Oct 2019 08:52:45 +0000 (08:52 +0000)]
SPMD: entry point info get helper
This patch provides a helper to get the entry_point_info
structure used by the boot CPU as it is used to initialise
the SPMC context on secondary CPUs.
Jacky Bai [Tue, 7 Jan 2020 03:05:22 +0000 (11:05 +0800)]
plat: imx8m: Fix the race condition during cpu hotplug
CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC register(A53_AD), so lock is necessary to do exlusive access.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I1296592e05fa78429c3f0fac066951521db755e3
Alexei Fedorov [Sun, 16 Aug 2020 15:01:13 +0000 (16:01 +0100)]
libc/memset: Implement function in assembler
Trace analysis of FVP_Base_AEMv8A model running in
Aarch32 mode with the build options listed below:
TRUSTED_BOARD_BOOT=1 GENERATE_COT=1
ARM_ROTPK_LOCATION=devel_ecdsa KEY_ALG=ecdsa
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
shows that when auth_signature() gets called
71.84% of CPU execution time is spent in memset() function
written in C using single byte write operations,
see lib\libc\memset.c.
This patch replaces C memset() implementation with assembler
version giving the following results:
- for Aarch32 in auth_signature() call memset() CPU time
reduced to 24.84%.
- Number of CPU instructions executed during TF-A
boot stage before start of BL33 in RELEASE builds:
----------------------------------------------
| Arch | C | assembler | % |
----------------------------------------------
| Aarch32 | 2073275460 | 1487400003 | -28.25 |
| Aarch64 | 2056807158 | 1244898303 | -39.47 |
----------------------------------------------
The patch also replaces memset.c with aarch64/memset.S
in plat\nvidia\tegra\platform.mk.
David Pu [Thu, 8 Aug 2019 21:20:03 +0000 (14:20 -0700)]
Tegra: common: make plat_psci_ops routines static
This patch makes Tegra platform psci ops routines to static. These
routines are called by PSCI framework and no external linkage is
necessary. This patch also fixes MISRA C-2012 Rule 8.6 violations.
Change-Id: Idd2381809f76dc0fd578c1c92c0f8eea124f2e88 Signed-off-by: David Pu <dpu@nvidia.com>
Masahisa Kojima [Thu, 11 Jun 2020 12:46:44 +0000 (21:46 +0900)]
qemu/qemu_sbsa: enable SPM support
Enable the spm_mm framework for the qemu_sbsa platform.
Memory layout required for spm_mm is created in secure SRAM.
Co-developed-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Fu Wei <fu.wei@linaro.org> Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a
Manish Pandey [Tue, 18 Aug 2020 11:02:15 +0000 (11:02 +0000)]
Merge changes from topic "soc-id" into integration
* changes:
plat/arm: juno: Implement methods to retrieve soc-id information
plat/arm: fvp: Implement methods to retrieve soc-id information
plat/arm: remove common code for soc-id feature
runtime_exceptions: Update AT speculative workaround
As per latest mailing communication [1], we decided to
update AT speculative workaround implementation in order to
disable page table walk for lower ELs(EL1 or EL0) immediately
after context switching to EL3 from lower ELs.
Previous implementation of AT speculative workaround is available
here: 45aecff00
AT speculative workaround is updated as below:
1. Avoid saving and restoring of SCTLR and TCR registers for EL1
in context save and restore routine respectively.
2. On EL3 entry, save SCTLR and TCR registers for EL1.
3. On EL3 entry, update EL1 system registers to disable stage 1
page table walk for lower ELs (EL1 and EL0) and enable EL1
MMU.
4. On EL3 exit, restore SCTLR and TCR registers for EL1 which
are saved in step 2.
el3_runtime: Rearrange context offset of EL1 sys registers
SCTLR and TCR registers of EL1 plays role in enabling/disabling of
page table walk for lower ELs (EL0 and EL1).
Hence re-arranged EL1 context offsets to have SCTLR and TCR registers
values one after another in the stack so that these registers values
can be saved and restored using stp and ldp instruction respectively.
Change-Id: Iaa28fd9eba82a60932b6b6d85ec8857a9acd5f8b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Also, changes are done to enable common macro 'ERRATA_SPECULATIVE_AT'
if AT speculative errata workaround is enabled for any of the above
CPUs using 'ERRATA_*' CPU specific build macro.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I3e6a5316a2564071f3920c3ce9ae9a29adbe435b
In case of AT speculative workaround applied, page table walk
is disabled for lower ELs (EL1 and EL0) in EL3.
Hence added a wrapper function which temporarily enables page
table walk to execute AT instruction for lower ELs and then
disables page table walk.
Execute AT instructions directly for lower ELs (EL1 and EL0)
assuming page table walk is enabled always when AT speculative
workaround is not applied.
Change-Id: I4ad4c0bcbb761448af257e9f72ae979473c0dde8 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
el3_runtime: Update context save and restore routines for EL1 and EL2
As per latest mailing communication [1], we decided
not to update SCTLR and TCR registers in EL1 and EL2 context
restore routine when AT speculative workaround is enabled
hence reverted the changes done as part of this commit: 45aecff00.
plat/arm: Use common build flag for using generic sp804 driver
SP804 TIMER is not platform specific, and current code base adds
multiple defines to use this driver. Like FVP_USE_SP804_TIMER and
FVP_VE_USE_SP804_TIMER.
This patch removes platform specific build flag and adds generic
flag `USE_SP804_TIMER` to be set to 1 by platform if needed.
Andre Przywara [Sun, 2 Aug 2020 23:25:21 +0000 (00:25 +0100)]
plat/allwinner: Only enable DRIVEVBUS if really needed
The DRIVEVBUS power rail of the AXP803 PMIC is mostly used to supply
the USB bus power on micro USB sockets, when used in host mode. As this
is a dynamic operation, and mostly we want micro USB sockets to act in
client mode initially, BL31 should not actually enable this power line.
However, on some boards DRIVEVBUS is used to supply power to normal
USB-A sockets. Failing to activate this line there results in
non-functional USB in U-Boot on those boards.
For that reason we were enabling DRIVEVBUS so far, as it did not seem to
cause any harm to the other boards. However it turns out that on the
Pinephone (and other systems with a battery), actually enabling DRIVEVBUS
unconditionally causes serious problems (reboot loop).
To accommodate both use cases, without reverting to a build time option,
check the default OTG configuration in the devicetree. For boards with
USB-A sockets this is set to "host", on boards with micro-B sockets to
"otg". Depending on this setting, we either enable DRIVEVBUS or leave it
alone.
This fixes TF-A on the Pinephone and potentially other battery powered
devices.
Change-Id: Iec0e07f218b2b4393bf4e05c3386261f8ed19e9f Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sun, 2 Aug 2020 23:25:03 +0000 (00:25 +0100)]
plat/allwinner: Use common gicv2.mk
Compiling BL31 for the Allwinner platform now produces a message about
the deprecation of gic_common.c.
Follow the advice and use include gicv2.mk instead.
Collect all includes at the beginning of the file on the way.
Change-Id: Iee46e21a630bfa831d28059f09aa7b049eb554bb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Manish Pandey [Fri, 14 Aug 2020 15:58:04 +0000 (15:58 +0000)]
Merge changes from topic "sp_dual_signing" into integration
* changes:
SPM: Add owner field to cactus secure partitions
SPM: Alter sp_gen.mk entry depending on owner of partition
plat/arm: enable support for Plat owned SPs
Ruari Phipps [Tue, 11 Aug 2020 14:28:03 +0000 (15:28 +0100)]
SPM: Add owner field to cactus secure partitions
For supporting dualroot CoT for Secure Partitions a new optional field
"owner" is introduced which will be used to sign the SP with
corresponding signing domain. To demonstrate its usage, this patch adds
owners to cactus Secure Partitions.
SPM: Alter sp_gen.mk entry depending on owner of partition
With recently introduced dualroot CoT for SPs where they are owned
either by SiP or by Platform. SiP owned SPs index starts at SP_PKG1_ID
while Plat owned SPs index starts at SP_PKG5_ID.
This patch modifies SP makefile generator script to take CoT as an
argument and if it is "dualroot" then generates SP_PKG in order
mentioned above, otherwise generates it sequentially.
For Arm platforms SPs are loaded by parsing tb_fw_config.dts and
adding them to SP structure sequentially, which in-turn is appended to
loadable image list.
With recently introduced dualroot CoT for SPs where they are owned
either by SiP or by Platform. SiP owned SPs index starts at SP_PKG1_ID
and Plat owned SPs index starts at SP_PKG5_ID. As the start index of SP
depends on the owner, there should be a mechanism to parse owner of a SP
and put it at the correct index in SP structure.
This patch adds support for parsing a new optional field "owner" and
based on it put SP details(UUID & Load-address) at the correct index in
SP structure.
Ensuring that each file changed by a patch has the correct copyright and
license information does not only apply to documentation files but to
all files within the source tree.
Move the guidance for copyright and license headers out of the paragraph
about updating the documentation to avoid any confusion.
Also do some cosmetic changes (adding empty lines, fitting in longer
lines in the 80-column limit, ...) to improve the readability of the RST
file.
doc: Stop advising the creation of Phabricator issues
We have noticed that Phabricator (the ticketing system on tf.org [1])
has far less visibility within the community than the mailing list [2].
For this reason, let's drop usage of Phabricator for anything else than
bug reports. For the rest, advise contributors to start a discussion on
the mailing list, where they are more likely to get feedback.
Jimmy Brisson [Wed, 5 Aug 2020 19:05:53 +0000 (14:05 -0500)]
Prevent colliding identifiers
There was a collision between the name of the typedef in the CASSERT and
something else, so we make the name of the typedef unique to the
invocation of DEFFINE_SVC_UUID2 by appending the name that's passed into
the macro. This eliminates the following MISRA violation:
bl1/bl1_main.c:233:[MISRA C-2012 Rule 5.6 (required)] Identifier
"invalid_svc_uuid" is already used to represent a typedef.
This also resolves MISRA rule 5.9.
These renamings are as follows:
* tzram -> secram. This matches the function call name as it has
sec_mem in it's name
* fw_config_base -> config_base. This file does not mess with
hw_conig, so there's little chance of confusion
Change-Id: I8734ba0956140c8e29b89d0596d10d61a6ef351e Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Olivier Deprez [Thu, 13 Aug 2020 10:55:54 +0000 (12:55 +0200)]
TF-A AMU: remove AMU enable info print
Following f3ccf036ecb1ae1628 the INFO print in amu_enable is causing
a lot of print outs on UART1 in DEBUG mode especially on PSCI test
cases because CPU_ON or SUSPEND operations call:
cm_prepare_el3_exit => enable_extensions_nonsecure => amu_enable.
PSCI SUSPEND is also very frequent in linux boot cases causing test
timeout failures.
dualroot: add chain of trust for Platform owned SPs
For dualroot CoT there are two sets of SP certificates, one owned by
Silicon Provider(SiP) and other owned by Platform. Each certificate can
have a maximum of 4 SPs.
This patch reduces the number of SiP owned SPs from 8 to 4 and adds
the remaining 4 to Plat owned SP.
Plat owned SP certificate is signed using Platform RoT key and
protected against anti-rollback using the Non-trusted Non-volatile
counter.
cert_create: add Platform owned secure partitions support
Add support to generate a certificate named "plat-sp-cert" for Secure
Partitions(SP) owned by Platform.
Earlier a single certificate file "sip-sp-cert" was generated which
contained hash of all 8 SPs, with this change SPs are divided into
two categories viz "SiP owned" and "Plat owned" containing 4 SPs each.
projects / arm-tf.git / log