Varun Wadekar [Mon, 30 Oct 2017 21:35:17 +0000 (14:35 -0700)]
Tegra: memctrl_v2: platform handler for TZDRAM settings
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.
Varun Wadekar [Tue, 17 Oct 2017 17:29:24 +0000 (10:29 -0700)]
Tegra186: sanity check target cluster during core power on
This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.
Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware
This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.
MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).
This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.
The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.
1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
non zero.
The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.
Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH
This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.
Tegra186: mce: get the "right" uncore command/response bits
This patch corrects the logic to read the uncore command/response bits
from the command/response values. The previous logic tapped into incorrect
bits leading to garbage counter values.
This patch modifies the timeout loop to use udelay() instead of
mdelay(). This helps with the boot time on some platforms which
issue a lot of MCE calls and every mdelay adds up increasing the
boot time by a lot.
To accommodate scenarios where we want to use a UART baud rate other than
the default 115,200 allow the associated compiler definition to be set
via the K3_USART_BAUD build option by updating the platform make file.
Since the platform make file now also contains the default value (still
115,200), go ahead and remove the redundant definition from the platform
header file.
Suggested-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Andrew F. Davis [Fri, 4 Jan 2019 18:49:16 +0000 (12:49 -0600)]
ti: k3: drivers: ti_sci: Clear receive queue before transmitting
Send and receive currently must be be serialized, any message already in
the receive queue when a new message is to be sent will cause a mismatch
with the expected response from this new message. Clear out all messages
from the response queue before sending a new request.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
Andrew F. Davis [Thu, 3 Jan 2019 19:23:52 +0000 (13:23 -0600)]
ti: k3: drivers: ti_sci: Add processor shutdown API
This is a pseudo-API command consisting of a wait processor status
command and a set device state command queued back-to-back without
waiting for the System Firmware to ACK either message.
This is needed as the K3 power down specification states the System
Firmware must wait for a processor to be in WFI/WFE before powering
it down. The current implementation of System Firmware does not provide
such a command. Also given that with PSCI the core to be shutdown is the
core that is processing the shutdown request, the core cannot itself wait
for its own WFI/WFE status. To workaround this limitation, we submit
a wait processor status command followed by the actual shutdown command.
The shutdown command will not be processed until the wait command has
finished. In this way we can continue to WFI before the wait command
status has been met or timed-out and the shutdown command is processed.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
Andrew F. Davis [Tue, 18 Dec 2018 19:21:12 +0000 (13:21 -0600)]
ti: k3: drivers: ti_sci: Add processor status wait API
This TI-SCI API can be used wait for a set of processor status flags to
be set or cleared. The flags are processor type specific. This command
will not return ACK until the specified status is met. NACK will be
returned after the timeout elapses or on error.
Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Nishanth Menon <nm@ti.com>
Harvey Hsieh [Mon, 21 Aug 2017 07:01:53 +0000 (15:01 +0800)]
Tegra: memctrl: clean MC INT status before exit to bootloader
This patch cleans the Memory controller's interrupt status
register, before exiting to the non-secure world during
cold boot. This is required as we observed that the MC's
arbitration bit is set before exiting the secure world.
Varun Wadekar [Wed, 23 Aug 2017 23:02:06 +0000 (16:02 -0700)]
Tegra: use 'PLATFORM_MAX_CPUS_PER_CLUSTER' to calculate core position
This patch updates the plat_my_core_pos() and platform_get_core_pos() helper
functions to use the `PLATFORM_MAX_CPUS_PER_CLUSTER` macro to calculate the
core position.
Harvey Hsieh [Wed, 9 Aug 2017 08:24:40 +0000 (16:24 +0800)]
Tegra: memctrl_v2: pack TZDRAM base into SCRATCH54_LO
This patch moves the TZDRAM base address to SCRATCH55_LO due
to security concerns. The HI and LO address bits are packed
into SCRATCH55_LO for the warmboot firmware to restore.
SCRATCH54_HI is still being used for backward compatibility,
but would be removed eventually.
The scratch registers are populated as:
* RSV55_0 = CFG1[12:0] | CFG0[31:20]
* RSV55_1 = CFG3[1:0]
* RSV54_1 = CFG1[12:0]
Varun Wadekar [Fri, 4 Aug 2017 00:17:00 +0000 (17:17 -0700)]
Tegra: enable 'WARMBOOT_ENABLE_DCACHE_EARLY' flag
This patch enables the 'WARMBOOT_ENABLE_DCACHE_EARLY' flag to enable
D-cache early, during the CPU warmboot sequence. This flag is applicable
for platforms like Tegra, which do not require interconnect programming to
enable cache coherency.
Samuel Payne [Fri, 16 Jun 2017 04:12:45 +0000 (21:12 -0700)]
Tegra210_B01: SC7: Select RNG mode based on ECID
If ECID is valid, we can use force instantiation
otherwise, we should use reseed for random data
generation for RNG operations in SE context save
DNI because we are not keeping software save
sequence in main.
Change-Id: I73d650e6f45db17b780834b8de4c10501e05c8f3 Signed-off-by: Samuel Payne <spayne@nvidia.com>
Varun Wadekar [Thu, 3 Jan 2019 00:30:01 +0000 (16:30 -0800)]
Tegra: trusty: pass profiling base to Trusted OS
* Previous boot loader passes Shared DRAM address
to be used by Trusted OS to dump its boot timing records
* This patch adds support to pass the parameter
to Trusted OS during cold boot
This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save routine is intended to be invoked from
the ATF SC7 entry.
Varun Wadekar [Thu, 3 Aug 2017 18:19:01 +0000 (11:19 -0700)]
Tegra210: increase number of dynamic memory mappings
This patch increases the MAX_MMAP_REGIONS build flag to allow
Tegra210 platforms to dynamically map multiple memory apertures
at the same time. This takes care of scenarios when we get multiple
requests to memmap memory apertures at the same time.
Tegra: lib: library for profiling the cold boot path
The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.
This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.
Original change by Akshay Sharan <asharan@nvidia.com>
Anthony Zhou [Wed, 26 Jul 2017 09:16:54 +0000 (17:16 +0800)]
Tegra: fix defects flagged by MISRA Rule 10.3
MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.
The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.
Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.
Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Harvey Hsieh [Thu, 15 Jun 2017 23:28:43 +0000 (16:28 -0700)]
Tegra210: save TZSRAM context from the "_wfi" handler
This patch saves the TZSRAM context and takes the SoC into System Suspend
from the "_wfi" handler. This helps us save the entire CPU context from
the TZSRAM, before entering System Suspend. In the previous implementation
we missed saving some part of the state machine context leading to an assert
on System Suspend exit.
Anthony Zhou [Fri, 7 Jul 2017 06:29:51 +0000 (14:29 +0800)]
Tegra: common: fix defects flagged by MISRA scan
Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the defects, if 'e' is not bool type.
Remove unused code [Rule 2.5]
Fix the essential type model violation [Rule 10.6, 10.7]
Use local parameter to raplace function parameter [Rule 17.8]
Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Samuel Payne [Mon, 12 Jun 2017 23:38:23 +0000 (16:38 -0700)]
Tegra210: se: disable SMMU before suspending SE block
This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU when we exit System Suspend.
Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d Signed-off-by: Samuel Payne <spayne@nvidia.com>
Anthony Zhou [Wed, 22 Mar 2017 06:42:42 +0000 (14:42 +0800)]
Tegra: pm: fix MISRA defects
Main fixes:
* Use int32_t replace int, use uint32_t replace unsign int
[Rule 4.6]
* Add function define to header file [Rule 8.4]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Voided non c-library functions whose return types are not used
[Rule 17.7]
Change-Id: Ifa3ba4e75046697cfede885096bee9a30efe6519 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Varun Wadekar [Wed, 24 May 2017 15:47:15 +0000 (08:47 -0700)]
Tegra186: reduce complexity for the 'get_target_pwr_state' handler
This patch reduces the code complexity for the platform's 'get_target_pwr_state'
handler, by reducing the number of 'if' conditions and adding helper functions
to calculate power state for the cluster/system.
Varun Wadekar [Wed, 28 Jun 2017 21:38:19 +0000 (14:38 -0700)]
Tegra: gpcdma: driver for general purpose DMA
This patch adds the driver for the general purpose DMA hardware
block on newer Tegra SoCs. The GPCDMA is a special purpose DMA
used to speed up memory copy operations to/from DRAM and TZSRAM.
This patch introduces a macro 'USE_GPC_DMA' to allow platforms
to override CPU based memory operations.
Samuel Payne [Thu, 15 Jun 2017 20:57:47 +0000 (13:57 -0700)]
Tegra210: SE: remove logic to enable atomic save/restore
This patch removes the logic to set the bit that enables atomic context
save/restore when we enter System suspend. The bootrom enables this bit
during cold boot and exit from System Suspend, so we can remove this
setting from the driver.
Change-Id: Id4e08d5048155c970f5e31d9c9dd676c07182ade Signed-off-by: Samuel Payne <spayne@nvidia.com>
Bryan O'Donoghue [Fri, 26 Oct 2018 15:06:28 +0000 (16:06 +0100)]
docs: warp7: Update WaRP7 description for TBB
This patch updates the WaRP7 build descriptions for booting WaRP7 in
Trusted Board Boot mode. TBB is the only mode we really intend to support
for this board so rather than maintain documentation for the old way of
doing it, this patch updates the description for TBB mode only.
Yann Gautier [Thu, 17 Jan 2019 13:52:47 +0000 (14:52 +0100)]
stm32mp1: add BSEC driver
The BSEC (Boot and Security and OTP control) is intended to control an OTP
(one time programmable) fuse box, used for on-chip non-volatile storage
for device configuration and security parameters.
Change-Id: I38c44684c7b9c6a1f24ec0ae3fe99cec481d5a51 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Mathieu Belou <mathieu.belou@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Yann Gautier [Thu, 17 Jan 2019 18:17:47 +0000 (19:17 +0100)]
stm32mp1: update device tree and gpio functions
Change fdt_check_status function to fdt_get_status.
Update GPIO defines.
Move some functions in gpio driver, instead of dt helper file.
Add GPIO bank helper functions.
Use only one status field in dt_node_info structure including both status
and secure status.
Change-Id: I34f93408dd4aac16ae722f564bc3f7d6ae978cf4 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Yann Gautier [Thu, 17 Jan 2019 13:41:46 +0000 (14:41 +0100)]
stm32mp1: update platform files
Move print_reset_reason function to bl2_plat_setup.c
Put __unused attribute for unused bl2_el3_early_platform_setup args.
Rename dt_dev_info to dt_uart_info.
Put MMU configuration earlier.
Remove unused macros.
Use U() or ULL() macros where needed.
Use device tree to configure GIC.
Use GIC helper function.
Yann Gautier [Thu, 17 Jan 2019 13:35:22 +0000 (14:35 +0100)]
drivers: st: update drivers code
Reword some traces.
Use uintptr_t where required.
Reduce scope of variables.
Improve io_stm32image algo.
Complete some IP registers definitions.
Add failure on supported DDR (stm32mp1_ddr_init()).
Fix cache flush on cache disable (stm32mp1_ddr_setup).
Change-Id: Ie02fa71e02b9d69abc807fd5b7df233e5be6668c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Yann Gautier [Thu, 17 Jan 2019 13:27:50 +0000 (14:27 +0100)]
drivers: st: pmic: update stpmic1 driver
Change-Id: I4a1b281925e0a3a1e2a34b3e363537e4a7f13823 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Bryan O'Donoghue [Thu, 29 Nov 2018 15:59:14 +0000 (15:59 +0000)]
warp7: Define DTB overlay address in memory map
This patch defines the expected DTB overlay address in the memory map for
this platform. Its important that all points in the boot process agree on
this memory map even if not all elements utilize it.
Bryan O'Donoghue [Thu, 29 Nov 2018 14:46:05 +0000 (14:46 +0000)]
warp7: io_storage: Remove DTB from FIP
Recently upstreamed changes to OP-TEE mean that it is possible for OP-TEE
to provide a DTB overlay directly to subsequent boot stages thus negating
the requirement to bundle a DTB in the FIP.
This patch switches off the dependency on the DTB in the FIP descriptor
instead we will provide the necessary data as an overlay from OP-TEE.
Anson Huang [Tue, 15 Jan 2019 02:56:36 +0000 (10:56 +0800)]
imx: add cpu-freq SIP runtime service support
On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock
rate is managed by SCFW(system controller firmware) and can ONLY be
changed from secure world, so SIP runtime service is needed for
setting CPU's clock rate, this patch adds cpu-freq SIP runtime service
support.
Anson Huang [Tue, 15 Jan 2019 02:34:04 +0000 (10:34 +0800)]
imx: add imx8qm/imx8qx SRTC SIP runtime service support
On i.MX8QM/i.MX8QX with system controller inside, the SRTC is
managed by SCFW(system controller firmware) and some functions
like setting SRTC's time etc. can ONLY be requested from secure
world, so SIP runtime service is needed for such kind of operations,
this patch adds SRTC SIP runtime service support for i.MX8QM and
i.MX8QX.
Anson Huang [Tue, 15 Jan 2019 02:22:06 +0000 (10:22 +0800)]
Support for NXP's i.MX8 SoCs timer IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Igor Opaniuk [Wed, 16 Jan 2019 21:59:41 +0000 (23:59 +0200)]
rpi3: fix RPI3_PRELOADED_DTB_BASE usage
In case if `RPI3_PRELOADED_DTB_BASE` isn't defined explicitly with
proper pre-loaded DTB address, `add_define` macro defined in
`make_helpers/build_macros.mk` still supplies this definition to the
compiler like `-DRPI3_PRELOADED_DTB_BASE`, and it's obviously is set to
default value 1.
This simply leads to the wrong `MAP_NS_DTB` region definition (base_va
is set `0x1` instead of `0x00010000`) in `plat/rpi3/rpi3_common.c`:
Which causes aligment check to fail in `mmap_add_region_check()`:
VERBOSE: base_pa: 0x00000001, base_va: 0x00000001, size: 0x00010000
...
ERROR: mmap_add_region_check() failed. error -22
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Sam Payne [Mon, 8 May 2017 19:42:49 +0000 (12:42 -0700)]
Tegra210: Enable ECC reporting for B01 SKUs
This patch enables L2 error correction and parity protection
for Tegra210 on boot and exit from suspend. The previous bootloader
sets the boot parameter, indicating ECC reporting, only for B01 SKUs.
Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c Signed-off-by: Sam Payne <spayne@nvidia.com>
Tegra210: skip the BTB invalidate workaround for B01 SKUs
This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file to
include macros, add proper guards to tegra_platform.h.
Krishna Reddy [Thu, 25 May 2017 18:04:33 +0000 (11:04 -0700)]
Tegra186: memctrl_v2: Set MC clients ordering as per client needs
Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part of BW issues debug.
SMMU Client config register are obsolete from T186. Clean up the unnecessary
register definitions and programming of these registers.
Cleanup unnecessary macros as well.
Varun Wadekar [Mon, 12 Jun 2017 23:47:16 +0000 (16:47 -0700)]
Tegra210: memmap all the IRAM memory banks
This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the banks to avoid surprises.
projects / arm-tf.git / log