This change ports the software based SE context save routines.
The software implements the context save sequence for SE/SE2 and
PKA1. The context save routine is intended to be invoked from
the ATF SC7 entry.
Varun Wadekar [Thu, 3 Aug 2017 18:19:01 +0000 (11:19 -0700)]
Tegra210: increase number of dynamic memory mappings
This patch increases the MAX_MMAP_REGIONS build flag to allow
Tegra210 platforms to dynamically map multiple memory apertures
at the same time. This takes care of scenarios when we get multiple
requests to memmap memory apertures at the same time.
Tegra: lib: library for profiling the cold boot path
The non secure world would like to profile the boot path for
the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
DRAM region (4K) is allocated and the base address is passed to
the EL3 firmware.
This patch adds a library to allow the platform code to store the
tag:timestamp pair to the shared memory. The tegra platform code
then uses the `record` method to add timestamps.
Original change by Akshay Sharan <asharan@nvidia.com>
Anthony Zhou [Wed, 26 Jul 2017 09:16:54 +0000 (17:16 +0800)]
Tegra: fix defects flagged by MISRA Rule 10.3
MISRA Rule 10.3, the value of an expression shall not be assigned to
an object with a narrower essential type or of a different essential
type category.
The essential type of a enum member is anonymous enum, the enum member
should be casted to the right type when using it.
Both UL and ULL suffix equal to uint64_t constant in compiler
aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix
in platform code. So in some case, cast a constant to uint32_t is
necessary.
Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Harvey Hsieh [Thu, 15 Jun 2017 23:28:43 +0000 (16:28 -0700)]
Tegra210: save TZSRAM context from the "_wfi" handler
This patch saves the TZSRAM context and takes the SoC into System Suspend
from the "_wfi" handler. This helps us save the entire CPU context from
the TZSRAM, before entering System Suspend. In the previous implementation
we missed saving some part of the state machine context leading to an assert
on System Suspend exit.
Anthony Zhou [Fri, 7 Jul 2017 06:29:51 +0000 (14:29 +0800)]
Tegra: common: fix defects flagged by MISRA scan
Macro assert(e) request 'e' is a bool type, if useing other
type, MISRA report a "The Essential Type Model" violation,
Add a judgement to fix the defects, if 'e' is not bool type.
Remove unused code [Rule 2.5]
Fix the essential type model violation [Rule 10.6, 10.7]
Use local parameter to raplace function parameter [Rule 17.8]
Change-Id: Ifce932addbb0a4b063ef6b38349d886c051d81c0 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Samuel Payne [Mon, 12 Jun 2017 23:38:23 +0000 (16:38 -0700)]
Tegra210: se: disable SMMU before suspending SE block
This patch disables SMMU hardware before suspending the SE
block, for the context save operation to complete. The NS
word will re-enable SMMU when we exit System Suspend.
Change-Id: I4d5cd982ea6780db5c38b124550d847e3928c60d Signed-off-by: Samuel Payne <spayne@nvidia.com>
Anthony Zhou [Wed, 22 Mar 2017 06:42:42 +0000 (14:42 +0800)]
Tegra: pm: fix MISRA defects
Main fixes:
* Use int32_t replace int, use uint32_t replace unsign int
[Rule 4.6]
* Add function define to header file [Rule 8.4]
* Added curly braces ({}) around if statements in order to
make them compound [Rule 15.6]
* Voided non c-library functions whose return types are not used
[Rule 17.7]
Change-Id: Ifa3ba4e75046697cfede885096bee9a30efe6519 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
Varun Wadekar [Wed, 24 May 2017 15:47:15 +0000 (08:47 -0700)]
Tegra186: reduce complexity for the 'get_target_pwr_state' handler
This patch reduces the code complexity for the platform's 'get_target_pwr_state'
handler, by reducing the number of 'if' conditions and adding helper functions
to calculate power state for the cluster/system.
Varun Wadekar [Wed, 28 Jun 2017 21:38:19 +0000 (14:38 -0700)]
Tegra: gpcdma: driver for general purpose DMA
This patch adds the driver for the general purpose DMA hardware
block on newer Tegra SoCs. The GPCDMA is a special purpose DMA
used to speed up memory copy operations to/from DRAM and TZSRAM.
This patch introduces a macro 'USE_GPC_DMA' to allow platforms
to override CPU based memory operations.
Samuel Payne [Thu, 15 Jun 2017 20:57:47 +0000 (13:57 -0700)]
Tegra210: SE: remove logic to enable atomic save/restore
This patch removes the logic to set the bit that enables atomic context
save/restore when we enter System suspend. The bootrom enables this bit
during cold boot and exit from System Suspend, so we can remove this
setting from the driver.
Change-Id: Id4e08d5048155c970f5e31d9c9dd676c07182ade Signed-off-by: Samuel Payne <spayne@nvidia.com>
Anson Huang [Tue, 15 Jan 2019 02:56:36 +0000 (10:56 +0800)]
imx: add cpu-freq SIP runtime service support
On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock
rate is managed by SCFW(system controller firmware) and can ONLY be
changed from secure world, so SIP runtime service is needed for
setting CPU's clock rate, this patch adds cpu-freq SIP runtime service
support.
Anson Huang [Tue, 15 Jan 2019 02:34:04 +0000 (10:34 +0800)]
imx: add imx8qm/imx8qx SRTC SIP runtime service support
On i.MX8QM/i.MX8QX with system controller inside, the SRTC is
managed by SCFW(system controller firmware) and some functions
like setting SRTC's time etc. can ONLY be requested from secure
world, so SIP runtime service is needed for such kind of operations,
this patch adds SRTC SIP runtime service support for i.MX8QM and
i.MX8QX.
Anson Huang [Tue, 15 Jan 2019 02:22:06 +0000 (10:22 +0800)]
Support for NXP's i.MX8 SoCs timer IPC
NXP's i.MX8 SoCs have system controller (M4 core) which takes
control of timer management, including watchdog, srtc and system
counter etc., other clusters like Cortex-A35 can send out command
via MU (Message Unit) to system controller for timer operation.
This patch adds timer IPC(inter-processor communication) support.
Igor Opaniuk [Wed, 16 Jan 2019 21:59:41 +0000 (23:59 +0200)]
rpi3: fix RPI3_PRELOADED_DTB_BASE usage
In case if `RPI3_PRELOADED_DTB_BASE` isn't defined explicitly with
proper pre-loaded DTB address, `add_define` macro defined in
`make_helpers/build_macros.mk` still supplies this definition to the
compiler like `-DRPI3_PRELOADED_DTB_BASE`, and it's obviously is set to
default value 1.
This simply leads to the wrong `MAP_NS_DTB` region definition (base_va
is set `0x1` instead of `0x00010000`) in `plat/rpi3/rpi3_common.c`:
Which causes aligment check to fail in `mmap_add_region_check()`:
VERBOSE: base_pa: 0x00000001, base_va: 0x00000001, size: 0x00010000
...
ERROR: mmap_add_region_check() failed. error -22
Signed-off-by: Igor Opaniuk <igor.opaniuk@linaro.org>
Sam Payne [Mon, 8 May 2017 19:42:49 +0000 (12:42 -0700)]
Tegra210: Enable ECC reporting for B01 SKUs
This patch enables L2 error correction and parity protection
for Tegra210 on boot and exit from suspend. The previous bootloader
sets the boot parameter, indicating ECC reporting, only for B01 SKUs.
Change-Id: I6927884d375a64c69e2f1e9aed85f95c5e3cb17c Signed-off-by: Sam Payne <spayne@nvidia.com>
Tegra210: skip the BTB invalidate workaround for B01 SKUs
This patch skips the BTB invalidate workaround for Tegra210-B01 chips, as
they have already been fixed in the hardware. To allow the .S file to
include macros, add proper guards to tegra_platform.h.
Krishna Reddy [Thu, 25 May 2017 18:04:33 +0000 (11:04 -0700)]
Tegra186: memctrl_v2: Set MC clients ordering as per client needs
Set MC Clients ordering as per the clients needs(ordered, BW, ISO/non-ISO)
based on the latest info received from HW team as a part of BW issues debug.
SMMU Client config register are obsolete from T186. Clean up the unnecessary
register definitions and programming of these registers.
Cleanup unnecessary macros as well.
Varun Wadekar [Mon, 12 Jun 2017 23:47:16 +0000 (16:47 -0700)]
Tegra210: memmap all the IRAM memory banks
This patch memmaps all the IRAM memory banks during boot. The BPMP
firmware might place the channels in any of the IRAMs, so it is better
to map all the banks to avoid surprises.
Anthony Zhou [Wed, 1 Mar 2017 04:47:37 +0000 (12:47 +0800)]
Tegra: sip_calls: fix defects flagged by MISRA scan
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Fri, 28 Dec 2018 21:50:20 +0000 (13:50 -0800)]
Tegra: Passing EKS size as boot arg to trusty
* EKS blob size was not passed by as a boot parameter
earlier. Its being passed now
* If EKS value sent by bootloader is non-zero
update the boot parameter from default value to the argument
passed by bootloader
Sam Payne [Mon, 15 May 2017 18:10:37 +0000 (11:10 -0700)]
Tegra210B01: initialize DRBG on boot and resume
DRBG must be initialized to guarantee SRK has a random
value during suspend. This patch add a sequence to generate
an SRK on boot and during resume for SE1 and SE2. This SRK
value is not saved to PMC scratch, and should be overwitten
during atomic suspend.
Change-Id: Id5e2dc74a1b462dd6addaec1709fec46083a6e1c Signed-off-by: Sam Payne <spayne@nvidia.com>
Varun Wadekar [Fri, 5 May 2017 16:20:59 +0000 (09:20 -0700)]
Tegra210: bpmp: power management interface
This patch adds the driver to communicate with the BPMP processor
for power management use cases. BPMP controls the entry into cluster
and system power states. The Tegra210 platform port queries the BPMP
to calculate the target state for the cluster. In case BPMP does not
allow CCx entry, the core enters a power down state.
Tegra210B01: SE1 and SE2/PKA1 context save (atomic)
This patch adds the implementation of the SE atomic context save
sequence. The atomic context-save consistently saves to the TZRAM
carveout; thus there is no need to declare context save buffer or
map MMU region in TZRAM for context save. The atomic context-save
routine is responsible to validate the context-save progress
counter, where CTX_SAVE_CNT=133(SE1)/646(SE2), and the SE error
status to ensure the context save procedure complete successfully.
Anthony Zhou [Wed, 1 Mar 2017 04:47:37 +0000 (12:47 +0800)]
Tegra: sip_calls: fix defects flagged by MISRA scan
Main fixes:
* Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses [Rule 20.7]
* Added explicit casts (e.g. 0U) to integers in order for them
to be compatible with whatever operation they're used in [Rule
10.1]
* Fix implicit widening of composite assignment [Rule 10.6]
Change-Id: Ia83c3ab6e4c8c03c19c950978a7936ebfc290590 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Harvey Hsieh [Wed, 23 Nov 2016 11:13:08 +0000 (19:13 +0800)]
Tegra: support to set the L2 ECC and Parity enable bit
This patch adds capability to read the boot flag to enable L2 ECC
and Parity Protection bit for the Cortex-A57 CPUs. The previous
bootloader sets this flag value for the platform.
Tegra: console clock settings for real/FPGA platforms
This patch sets up the clock for the UART console, for real Silicon
and FPGA platforms. FPGA platforms run the UART clock source at
13MHz, whereas the clock cource runs at 408MHz for real silicon.
Anthony Zhou [Wed, 22 Mar 2017 06:37:04 +0000 (14:37 +0800)]
Tegra: platform: support simulation platforms and MISRA fixes
This patch adds support for simulation platforms as well as
fixes issues flagged by the MISRA scans.
Main MISRA fixes:
* Added explicit casts (e.g. 0U) to integers in order for them to be
compatible with whatever operation they're used in [Rule 10.1]
* Fix return type doesn't match the function type [Rule 10.3]
* Use single return point instead of multiple [Rule 15.5]
* Change return type for the tegra_platform_is_x handlers to bool
Change-Id: I871b7c37b22942f6c0c2049c14cc626d4a24d81c Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Ard Biesheuvel [Sat, 29 Dec 2018 18:44:35 +0000 (19:44 +0100)]
plat/synquacer: enable SPM support
Enable the deprecated SPM framework for the SynQuacer platform.
It involves creating a memory layout in secure DRAM, and wiring
up the SPM infrastructure so that the secure partition payload
that is loaded into this region by the SCP firmware is dispatched
appropriately.
Ard Biesheuvel [Sat, 29 Dec 2018 18:40:31 +0000 (19:40 +0100)]
plat/synquacer: enable OP-TEE logic only if SPD_opteed is set
The logic that initializes the BL32 entry point data structure
should only be executed if we are in fact loading OP-TEE, and
not if BL32_BASE is set for other reasons (i.e., when enabling
SPM)
Ard Biesheuvel [Sun, 6 Jan 2019 09:07:24 +0000 (10:07 +0100)]
spm: permit platform to override the VMA placement of the vector table
On some systems, it may be preferred to place the secure EL1/0 vector
table outside of the static placement of the BL31 image itself, for
instance when the latter is located in non-shareable SRAM which does
not tolerate inner shareable WBWA mappings (as is the case on SynQuacer)
So permit the platform to #define SPM_SHIM_EXCEPTIONS_VMA in its
supplementary linker script, in which case it will be used as the
VMA region for the vector table. Note that the LMA does not change,
and it is up to the platform to copy the contents to the right place
at init time.
Ard Biesheuvel [Thu, 3 Jan 2019 11:03:49 +0000 (12:03 +0100)]
services/spm_deprecated: disable alignment checking for S-EL0
Permit unaligned accesses while executing the secure partition
payload, so that we don't have to modify existing code that we
will host there. (The UEFI spec explicitly permits unaligned
accesses)
From now on, platform_def.h must include any header with definitions that
are platform-specific (like arm_def.h) and the included headers mustn't
include back platform_def.h, and shouldn't be used by other files. Only
platform_def.h should be included in other files. This will ensure that all
needed definitions are present, rather than needing to include all the
headers in all the definitions' headers just in case.
This also prevents problems like cyclic dependencies.
Change-Id: I9d3cf4d1de4b956fa035c79545222697acdaf5ca Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Anson Huang [Tue, 15 Jan 2019 06:27:10 +0000 (14:27 +0800)]
imx: make imx uart work for debug mode
With DEBUG_CONSOLE enabled, build will fail for imx8mq platform:
./build/imx8mq/release/bl31/imx8mq_bl31_setup.o:
In function `bl31_early_platform_setup2':
imx8mq_bl31_setup.c:(.text.bl31_early_platform_setup2+0x40):
undefined reference to `console_uart_register'
Makefile:741: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed
make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1
Besides, the .console_flush callback needs to be added to avoid
panic when debug mode is enabled, since the console_flush() will
call it without checking whether the function callback is valid.
Anson Huang [Tue, 15 Jan 2019 05:53:03 +0000 (13:53 +0800)]
imx: add necessary lpuart console_flush callback for debug
Current lpuart driver does NOT implement .console_flush callback,
if debug console is enabled, the console_flush() will call the
undefined .console_flush callback(NULL) for lpuart and leak to
panic, this patch adds .console_flush callback to make lpuart work
for debug mode.
Paul Beesley [Thu, 10 Jan 2019 16:14:04 +0000 (16:14 +0000)]
doc: Minor readme structure improvements
Improves wording and sentence structure of the readme, including:
- Using "TF-A" in place of "the TF-A" in a couple of places
- "Support for X" in place of "Support X"
- Explicitly naming the Secure Payload Dispatcher when introducing the
SPD acronym.
Change-Id: I4e7b7e7dc6748f631d07c02d97adcca10ae60ea4 Signed-off-by: Paul Beesley <paul.beesley@arm.com>
ARMv8.2-TTCNP is mandatory from ARMv8.2 onwards, but it can be implemented
in CPUs that don't implement all mandatory 8.2 features (and so have to
claim to be a lower version).
This patch removes usage of the ARM_ARCH_AT_LEAST() macro and uses system
ID registers to detect whether it is needed to set the bit or not.
Change-Id: I7bcbf0c7c937590dfc2ca668cfd9267c50f7d52c Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Joel Hutton [Wed, 28 Nov 2018 11:09:24 +0000 (11:09 +0000)]
hikey960: Increase max xlat tables
It is cleaner to use the same number of tables regardless of whether
OP-TEE is used or not. This doesn't result in a significant memory
usage increase.
Change-Id: I38bcaa3f2f197c0a352153117592749f189a265c Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Jolly Shah [Wed, 9 Jan 2019 20:37:57 +0000 (12:37 -0800)]
xilinx: Move IPI functions to common file
pm_service ipi functions can be used by other xilinx
platforms. So move it to common directory. Also change
node_id member type in pm_proc structure so it can be
used for versal where device IDs are used instead of
node IDs.
To accommodate this change header files are re-organized.
Jolly Shah [Mon, 7 Jan 2019 20:53:32 +0000 (12:53 -0800)]
xilinx: pm_service: Rename macros to use generic macro names
ZynqMP pm_service ipi file uses platform specific macros names.
pm_service ipi functions can be used by other Xilinx platforms
also. Make rename macros to use generic names so that it can be
used by common file.
pm_service ipi functions will be moved to common file in next patch.
Jolly Shah [Tue, 8 Jan 2019 19:27:36 +0000 (11:27 -0800)]
xilinx: Remove platform specific dependency from IPI function
ipi_mb function uses platform specific ipi configuration table.
These ipi_mb functions can be used for other Xilinx platform.
So, instead of using direct data structure, initialize IPI
configuration data by passing platform specific ipi table.
Macros are updated accordingly for this ipi table change.
This change is done so that ipi_mb functions can be moved to
common file without major changes. All common functions now would
be moved to common file in next patch.
Jolly Shah [Tue, 8 Jan 2019 19:25:28 +0000 (11:25 -0800)]
xilinx: Move ipi configuration structure definition to header file
Move ipi configuration structure definition to common header file
and rename it to common name, so it can be used for Xilinx specific
other platforms in upcoming changes.
Jolly Shah [Tue, 8 Jan 2019 19:21:29 +0000 (11:21 -0800)]
xilinx: zynqmp: Move zynqmp_ipi.h to include directory
Move zynqmp_ipi.h to platform specific include directory.
Rename it to plat_ipi.h instead of platform name. So, it can
be used to common source files which needs platform specific
data.
Jolly Shah [Tue, 8 Jan 2019 19:10:47 +0000 (11:10 -0800)]
plat: xilinx: zynqmp: Move zynqmp_private.h to include directory
Move zynqmp_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.
Joel Hutton [Tue, 8 Jan 2019 15:18:28 +0000 (15:18 +0000)]
juno:Fix CSS_USE_SCMI_SDS_DRIVER=0 configuration
A previous commit 89f2e589856f ("plat/arm: remove weak implemention of
'plat_arm_psci_override_pm_ops' function") introduced a problem with the
CSS_USE_SCMI_SDS_DRIVER configuration. In juno_pm.c the
css_scmi_override_pm_ops function was used regardless of whether the
flag was set. This patch ifdefs the function to restore the original
behaviour.
Change-Id: I508025ba70cf3a9250cc6270c1df209179c37ae7 Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Ard Biesheuvel [Tue, 1 Jan 2019 10:01:41 +0000 (11:01 +0100)]
services/spm_deprecated: permit timer sysreg access at S-EL0
Expose the timer registers that are accessible at EL0 per the
architecture to the SPM payload running in secure EL0. Note
that this requires NS_TIMER_SWITCH to be enable for all users
of this code.
projects / arm-tf.git / log