For peripheral where both status and secure-status are set to okay,
the function fdt_get_status() returns the same status (DT_SHARED) if
secure-status property is omitted. This secure-status property can then
be removed in boards DT files for iwdg nodes.
Johann Neuhauser [Wed, 13 Jul 2022 10:04:21 +0000 (12:04 +0200)]
feat(stm32mp15-fdts): add Avenger96 board with STM32MP157A DHCOR SoM
This should replace the stm32mp157a-avenger96.dts with the new device
tree files split into the STM32MP15 DHCOR SoM definition and the
Avenger96 baseboard like it's done in Linux and U-Boot.
Differences to stm32mp157a-avenger96.dts:
- Enable sdmmc2 for booting from eMMC
- improved clock settings like in U-Boot commit b6055945
"ARM: dts: stm32: Adjust PLL4 settings on AV96 again"
- improved DDR settings for DHSOMs like in U-Boot commit 92ca0f74
"ARM: dts: stm32: Synchronize DDR setttings on DH SoMs"
TF-A with this new dts(i) files on this board was fully tested with
the latest OP-TEE developer setup.
Change-Id: I85ce8eca7747965af3555fc19fd7b192dc3e5740 Signed-off-by: Johann Neuhauser <jneuhauser@dh-electronics.com>
Olivier Deprez [Thu, 25 Aug 2022 14:28:09 +0000 (16:28 +0200)]
Merge changes from topic "ffa_el3_spmc" into integration
* changes:
feat(tsp): enable test cases for EL3 SPMC
feat(tsp): increase stack size for tsp
feat(tsp): add ffa_helpers to enable more FF-A functionality
Marc Bonnici [Thu, 23 Dec 2021 20:14:34 +0000 (20:14 +0000)]
feat(tsp): enable test cases for EL3 SPMC
Introduce initial test cases to the TSP which are
designed to be exercised by the FF-A Test Driver
in the Normal World. These have been designed to
test basic functionality of the EL3 SPMC.
These tests currently ensure the following functionality:
- Partition discovery.
- Direct messaging.
- Communication with a Logical SP.
- Memory Sharing and Lending ABIs
- Sharing of contiguous and non-contiguous memory regions.
- Memory region descriptors spread of over multiple
invocations.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: Iaee4180aa18d6b7ac7b53685c6589f0ab306e876
Marc Bonnici [Thu, 23 Dec 2021 20:14:02 +0000 (20:14 +0000)]
feat(tsp): add ffa_helpers to enable more FF-A functionality
Include ffa_helpers originally taken from the TF-A Tests repo
to provide support for additional FF-A functionality.
Change-Id: Iacc3ee270d5e3903f86f8078ed915d1e791c1298 Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Akram Ahmad [Tue, 19 Jul 2022 13:38:46 +0000 (14:38 +0100)]
fix(errata): workaround for Cortex-A78C erratum 2395411
Cortex-A78C erratum 2395411 is a Cat B erratum that affects
revisions r0p1 and r0p2, and is currently open. The workaround
is to set CPUACTLR2_EL1[40] to 1, which will disable folding
of demand requests into older prefetches with L2 miss requests
outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2004089/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4f0fb278ac20a2eb4dd7e4efd1b1246dd85e48c4
Akram Ahmad [Fri, 22 Jul 2022 15:20:44 +0000 (16:20 +0100)]
fix(errata): workaround for Cortex-A510 erratum 2371937
Cortex-A510 erratum 2371937 is a Cat B erratum that applies
to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is
fixed in r1p2. The workaround is to set the ATOM field of
CPUECTLR_EL1 (bits [40:38]) to 0b010, which will force all
cacheable atomic operations to be executed near.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1873351/latest
https://developer.arm.com/documentation/SDEN1873361/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: Ia219a609a3397e39631de65831ecff8a3cd1227e
Achin Gupta [Mon, 4 Oct 2021 19:13:36 +0000 (20:13 +0100)]
feat(tsp): add FF-A support to the TSP
This patch adds the FF-A programming model in the test
secure payload to ensure that it can be used to test
the following spec features.
1. SP initialisation on the primary and secondary cpus.
2. An event loop to receive direct requests and respond
with direct responses.
3. Ability to receive messages that indicate power on
and off of a cpu.
4. Ability to handle a secure interrupt.
Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com> Signed-off-by: Shruti <shruti.gupta@arm.com>
Change-Id: I81cf744904d5cdc0b27862b5e4bc6f2cfe58a13a
Akshay Belsare [Tue, 23 Aug 2022 06:09:35 +0000 (11:39 +0530)]
fix(zynqmp): fix for incorrect afi write mask value
Currently, the AFIFM6_WRCTRL bus-width configuration is not happening
correctly due to the wrong register write mask value. To fix this issue
updated the mask value handling logic.
Akram Ahmad [Thu, 21 Jul 2022 14:25:08 +0000 (15:25 +0100)]
fix(errata): workaround for Cortex-A710 erratum 2147715
Cortex-A710 erratum 2147715 is a Cat B erratum that applies
to revision r2p0 of the CPU, and is fixed in r2p1. The work-
around is to set CPUACTLR_EL1[22]=1. Setting this will cause
the CFP instruction to invalidate all branch predictor resources
regardless of the context.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I94771bc1fc9b65a0c17d75200ec2b1df8a3279c6
Marc Bonnici [Tue, 23 Nov 2021 14:47:40 +0000 (14:47 +0000)]
feat(fvp/tsp_manifest): add example manifest for TSP
Add an example manifest for the EL3 SPMC on the FVP Platform
that allows booting the TSP example partition.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ie7f40328e0313abb5b1a121dfdc22a5f7387587f Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Marc Bonnici [Mon, 6 Jun 2022 13:37:57 +0000 (14:37 +0100)]
fix(spmc): fix relinquish validation check
The current implementation expects that the endpoint IDs of all
participants of a memory transaction to be listed in the relinquish
descriptor. As per the FF-A spec, aside from the current partition
ID, only the IDs of stream endpoints whose behalf it is relinquishing
the memory region must be specified.
The current implementation does not currently support proxy endpoints
therefore ensure that the endpoint count is always equal to 1 and
no stream endpoint IDs are specified and instead just verify the
caller is a valid participant in the memory transaction.
Additionally reuse the updated check in the retrieve request flow
for additional verification.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I3b970196af8a16b2531607775398cb8a2473793b
Juan Pablo Conde [Tue, 12 Jul 2022 20:40:29 +0000 (16:40 -0400)]
feat(rng-trap): add EL3 support for FEAT_RNG_TRAP
FEAT_RNG_TRAP introduces support for EL3 trapping of reads of the
RNDR and RNDRRS registers, which is enabled by setting the
SCR_EL3.TRNDR bit. This patch adds a new build flag
ENABLE_FEAT_RNG_TRAP that enables the feature.
This feature is supported only in AArch64 state from Armv8.5 onwards.
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: Ia9f17aef3444d3822bf03809036a1f668c9f2d89
Yann Gautier [Mon, 9 May 2022 15:01:11 +0000 (17:01 +0200)]
feat(stm32mp1): manage STM32MP13 rev.Y
The new SoC version for STM32MP13 is the revision Y. The register
SYSCFG_IDC is updated for this new version with the value 0x1003.
The function stm32mp_get_soc_name() should also be updated to manage
this new SoC revision.
Yann Gautier [Mon, 2 May 2022 09:12:43 +0000 (11:12 +0200)]
fix(stm32mp13-fdts): cleanup DT files
Instead of adding all peripheral nodes in SoC DT files, and then
removing them with BL2 overlay file, just remove them from SoC files.
And remove peripherals that are not used in TF-A on STM32MP13.
Yann Gautier [Mon, 2 May 2022 11:49:58 +0000 (13:49 +0200)]
fix(stm32mp13-fdts): align sdmmc pins with kernel
Update the pinctrl nodes for sdmmc instances in stm32mp13-pinctrl.dtsi
file to align with Linux. The boards DT files then need to be updated
accordingly.
Akram Ahmad [Mon, 18 Jul 2022 11:27:29 +0000 (12:27 +0100)]
fix(errata): workaround for Neoverse-N2 erratum 2376738
Neoverse-N2 erratum 2376738 is a Cat B erratum that applies
to revision r0p0 of the CPU. It is fixed in r0p1. The workaround
is to set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
behave like PLD/PRFM LD and not cause invalidations to other
PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Akram Ahmad <Akram.Ahmad@arm.com>
Change-Id: I4ad4434f9b7210244e67046d9657d218857dced5
Yann Gautier [Tue, 3 May 2022 13:37:54 +0000 (15:37 +0200)]
feat(st-sdmmc2): make reset property optional
Although not recommended, the reset property could be made optional.
This way the driver will probe even if no reset property is provided
in an sdmmc node in DT. This reset is already optional in Linux.
Yann Gautier [Wed, 12 Jun 2019 13:48:05 +0000 (15:48 +0200)]
feat(st-sdmmc2): manage CMD6
For SD-cards, CMD6 is used to switch functions, like setting high speed
mode. As it has another meaning for eMMC, and may not work on standard
capacity SD-cards, it must be checked with MMC_IS_SD_HC flag.
As ACMD6 is also used, and will have the same index, a check on
CMD/ACMD commands is done: a boolean is stored depending on previous
command. It is set to true if CMD55 is issued, for other commands
it is set to false.
Yann Gautier [Wed, 12 Jun 2019 13:55:37 +0000 (15:55 +0200)]
feat(mmc): manage SD Switch Function for high speed mode
On SD-cards, Switch Function Command (CMD6) is used to switch
functions, like setting High Speed mode. It is useful for high capacity
cards to double frequency (from 25MHz by default to 50MHz).
If the SD-card is High Capacity, a CMD6 is issued after filling the
device information. If High Speed mode is supported and the switch is
OK, then the max_bus_freq can be set to 50MHz. The driver set_ios()
function should then be called to update peripheral configuration,
especially clock prescaler.
Samuel Holland [Sat, 9 Apr 2022 03:22:04 +0000 (22:22 -0500)]
fix(build): discard sections also with SEPARATE_NOBITS_REGION
Some linker sections are discarded since 511046eaa28f ("BL31: discard
.dynsym .dynstr .hash sections to make ENABLE_PIE work"). However, that
logic was placed inside a preprocessor condition, so it only applied to
the !SEPARATE_NOBITS_REGION case. Move the /DISCARD/ block down so it
applies in all cases.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I6604609f2321a2a9c32a25721a697c320108a974
Samuel Holland [Sat, 9 Apr 2022 02:56:02 +0000 (21:56 -0500)]
fix(build): disable default PIE when linking
Commit f7ec31db2d ("Disable PIE compilation option") allowed building a
non-relocatable firmware with a default-PIE toolchain by disabling PIE
at compilation time. This prevents the compiler from generating
relocations against a GOT.
However, when a default-PIE GCC is used as the linker, the final binary
will still be a PIE, containing an (unused) GOT and dynamic symbol
table. These structures do not affect execution, but they waste space in
the firmware binary. Disable PIE at link time to recover this space.
Change-Id: I2be7ac9c1a957f6db8d75efe6e601e9a5760a925 Signed-off-by: Samuel Holland <samuel@sholland.org>
The purpose of including vendor extend plat.ld.rodata.inc
linker script is for compactly collecting vendor rodata in
intrinsic rodata section.
If vendors define a standalone section and assign the section
placed after __RW_END__, the raw bindry(bl31.bin) will include
bss section with zero value and increase binary size.
Signed-off-by: Leon Chen <leon.chen@mediatek.com>
Change-Id: I46dd8b02bfb26af1dcca27f61b3ea29ca74bbbd6
Juan Pablo Conde [Mon, 28 Feb 2022 19:14:44 +0000 (14:14 -0500)]
fix(errata): workaround for Neoverse-V1 erratum 1618635
Neoverse-V1 erratum 1618635 is a Cat B erratum that applies to
revision r0p0. It is fixed in r1p0.
The workaround is done through the instruction patching
mechanism, which is performed by a write sequence of
IMPLEMENTATION DEFINED registers.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401781/latest/
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
Change-Id: I53e406735cd3a2a930fdc72ebce3bbed97100168
Jamie Fox [Tue, 2 Aug 2022 14:39:21 +0000 (15:39 +0100)]
fix(lib/psa): update measured boot handle
When the measured boot service was upstreamed to TF-M, its static
handle was reallocated into the user partitions range. This change
updates the static handle here to make the service accessible.
Also removes the SIDs and Versions, since they are unused when a
service is accessed through a stateless handle, which encodes both
service ID and version. The attestation and measured boot services
only support access through their handles.
Signed-off-by: Jamie Fox <jamie.fox@arm.com>
Change-Id: I9d2ff1aad19470728289d574be3d5d11bdabeef4
Currently Tf-A uses whatever openssl binary is on the system to sign
images. However if OPENSSL_DIR is specified in the build flags this can
lead to linking issues as the system binary can end up being linked
against shared libraries provided in OPENSSL_DIR/lib if both binaries
(the system's and the on in OPENSSL_DIR/bin) are the same version.
This patch ensures that the binary used is always the one given by
OPENSSL_DIR to avoid those link issues.
Varun Wadekar [Wed, 3 Aug 2022 11:01:36 +0000 (12:01 +0100)]
fix(bl31): pass the EA bit to 'delegate_sync_ea'
During a synchronous exception, the 'enter_lower_el_sync_ea' handler
tests the ESR_EL3 EA bit and calls 'report_unhandled_exception', if
it is not set.
EA = 0 and IFSC = SEA, seems to be a contradiction. EA provides further
classification of a synchronous abort. A synchronous abort is determined
by the IFSC value on an instruction fetch synchronous abort. As a result,
EA will never be set to 1 on an instruction fetch synchronous abort and
'report_unhandled_exception' should not be called.
This patch removes this behavior to allow the platform to handle the
exception.
Signed-off-by: Nicolas Benech <nbenech@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3f004447ad4316d81649063e1ffb3ac644c83ede
Merge changes from topic "st_fip_uuid" into integration
* changes:
feat(stm32mp1): retrieve FIP partition by type UUID
feat(guid-partition): allow to find partition by type UUID
refactor(stm32mp1): update PLAT_PARTITION_MAX_ENTRIES
Michal Simek [Thu, 21 Jul 2022 06:54:16 +0000 (08:54 +0200)]
fix(versal): remove clock related macros
TF-A doesn't configure clock on Versal. Setup is done by previous
bootloader (called PLM) that's why there is no need to have macro listed in
headers. Also previous phase can disable access to these registers that's
why better to remove them.
Change-Id: I53ba344ad932c532b0babdce9d2b26e4c2c1b846 Signed-off-by: Michal Simek <michal.simek@amd.com>
Fixed below MISRA failure -
>>> CID 379362: Memory - illegal accesses (OVERRUN)
>>> Overrunning array "psci_non_cpu_pd_nodes" of 5 16-byte
>>> elements at element index 5 (byte offset 95) using index
>>> "i" (which evaluates to 5).
Change-Id: Ie88fc555e48b06563372bfe4e51f16b13c0a020b Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Bipin Ravi [Tue, 12 Jul 2022 22:13:01 +0000 (17:13 -0500)]
fix(errata): workaround for Cortex-X2 erratum 2371105
Cortex-X2 erratum 2371105 is a cat B erratum that applies to
revisions r0p0 - r2p0 and is fixed in r2p1. The workaround is to
set bit[40] of CPUACTLR2_EL1 to disable folding of demand requests
into older prefetches with L2 miss requests outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ib4f0caac36e1ecf049871acdea45526b394b7bad
projects / arm-tf.git / log