Thomas Abraham [Fri, 7 Dec 2018 04:28:50 +0000 (09:58 +0530)]
sgi/sgm: add a second maintainer for Arm's SGI and SGM platforms
Add a second maintainer for Arm's SGI and SGM platform support in
trusted firmware to handle the review and maintenance of
existing and upcoming platforms.
Change-Id: Ie7fa8da280d9351f7543122fb261d6ac6c7e15ad Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Soby Mathew [Thu, 17 Jan 2019 14:57:54 +0000 (14:57 +0000)]
GICv3: Allow probe for fewer GICR interfaces than exposed by the frame
Previously the GICv3 redistributor probe function
(gicv3_rdistif_base_addrs_probe()) asserted that the number of
per-CPU redistributor interfaces expected to be probed by the
platform is equal to the number exported by the redistributor
frame. This is a problem in case the number of CPUs in the
platform is less than the number of redistributor interfaces
in the frame. Hence this patch removes the assertion check
and allows probe for fewer redistributor interfaces as required
by the platform.
This commit adds SDHost driver for RaspberryPi3. SDHost driver uses the
GPIO driver to connect the SDCard and SDHost. By using this driver it is
able to read/write raw blocks on SDCard.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Sathees Balya [Fri, 25 Jan 2019 11:36:01 +0000 (11:36 +0000)]
lib/xlat_tables: Add support for ARMv8.4-TTST
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and
VSTCR_EL2.
This feature is supported in AArch64 state only.
This patch adds support for this feature to both versions of the
translation tables library. It also removes the static build time
checks for virtual address space size checks to runtime assertions.
Paul Beesley [Mon, 21 Jan 2019 12:06:24 +0000 (12:06 +0000)]
doc: Link coding guidelines to user guide
Adds a link from user-guide.rst to coding-guidelines.rst and merges
the information about using checkpatch from both files into the user
guide document.
Change-Id: Iffbb4225836a042d20024faf28b8bdd6b2c4043e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley [Thu, 17 Jan 2019 15:44:37 +0000 (15:44 +0000)]
doc: Add Coding Guidelines document
This content has been imported and adapted from the TF GitHub wiki
article 'ARM-Trusted-Firmware-Coding-Guidelines'.
The aim is to increase the visibility of the coding guidelines by
including them as part of the documentation that is within the TF
repository.
Additionally, the documentation can then be linked to by other
documents in the docs/ directory without worrying about broken links
to, for example, the external wiki.
Change-Id: I9d8cd6b5117b707c1a113baeba7fc5e1b4bf33bc Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Andre Przywara [Tue, 29 Jan 2019 09:25:14 +0000 (09:25 +0000)]
tools/fiptool: Fix UUID parsing in blob handling
Commit 033648652f ("Make TF UUID RFC 4122 compliant") changed the scanf
parsing string to handle endianness correctly.
However that changed the number of items sscanf handles, without
adjusting the sanity check just below.
Increase the expected return value from 11 to 16 to let fiptool handle
UUIDs given as blob parameters correctly again.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Method cpld_reset_cpu of bl31 is called from the Linux kernel and uses
GPIO6, GPIO2 pins as SPI bus lines to control the CPLD device. But in the
kernel GPIO6_8 pin are initialized to work in interrupt mode instead of
the input/output mode. This leads to the fact that the SPI bus becomes
non-functional. In this patch we switch the GPIO6_8 pin back to the
input-output mode.
Signed-off-by: Sergii Boryshchenko <sergii.boryshchenko@globallogic.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Tue, 29 Jan 2019 05:06:08 +0000 (06:06 +0100)]
Revert "rcar_gen3: plat: Enable programmable CPU reset address"
This reverts commit d48536e2f92d47ebb92cf12b35133c3be2d0e459,
which misbehaves on R-Car H3 ES2.0. Until the reason for that
misbehavior is understood, revert the commit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Anson Huang [Thu, 24 Jan 2019 08:50:02 +0000 (16:50 +0800)]
imx: power optimization for i.mx8qx
Current implementation of i.MX8QX power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.
To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.
If resources are powered off for suspend, they should be restored
properly after system resume.
Anson Huang [Thu, 24 Jan 2019 08:09:52 +0000 (16:09 +0800)]
imx: power optimization for i.mx8qm
Current implementation of i.MX8QM power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.
To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.
If resources are powered off for suspend, they should be restored
properly after system resume.
After the removal of deprecated interfaces in TF 2.0 the migration to
the new GIC driver interfaces was done incorrectly in rk3328 and rk3368: 2d6f1f01b141 ("rockchip: Migrate to new interfaces").
In the GICv2 driver it is mandated that all interrupts are Group 0
interrupts. This patch simply moves all Group 1 interrupts to Group 0.
Change-Id: I224c0135603eb5b81bd512976361500c0d129a91 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
plat/arm: Move dynamic xlat enable logic to makefile
The PLAT_XLAT_TABLES_DYNAMIC build option, defined in platform_def.h
in Arm platforms, is checked by several headers, affecting their
behaviour. To avoid issues around the include ordering of the headers,
the definition should be moved to the platform's makefile.
Change-Id: I0e12365c8d66309122e8a20790e1641a4f480a10 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Use full include paths like it is done for common includes.
This cleanup was started in commit d40e0e08283a ("Sanitise includes
across codebase"), but it only cleaned common files and drivers. This
patch does the same to Arm platforms.
Change-Id: If982e6450bbe84dceb56d464e282bcf5d6d9ab9b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
David Lin [Thu, 24 Jan 2019 22:15:57 +0000 (14:15 -0800)]
spd: trusty: trusty_setup should bail on unknown image
When an unknown Trusty image is found, there's no point of still trying
to register the BL32 init handler. Instead, we just should bail out of
the trusty_setup() and allow the system to continue to boot.
Manish Pandey [Mon, 21 Jan 2019 14:50:10 +0000 (14:50 +0000)]
Make device tree pre-processing similar to U-boot/Linux
Following changes are done to make DT pre-processing similar to that of
U-boot/Linux kernel.
1. Creating seperate CPPFLAGS for DT preprocessing so that compiler
options specific to it can be accommodated.
e.g: "-undef" compiler option avoids replacing "linux" string(used in
device trees) with "1" as "linux" is a pre-defined macro in gnu99
standard.
2. Replace CPP with PP for DT pre-processing, as CPP in U-boot/Linux is
exported as "${CROSS_COMPILE}gcc -E" while in TF-A it is exported as
"${CROSS_COMPILE}cpp".
Dilan Lee [Fri, 27 Oct 2017 01:51:09 +0000 (09:51 +0800)]
Tegra: add 'late' platform setup handler
This patch adds a platform setup handler that gets called after
the MMU is enabled. Platforms wanting to make use of this handler
should declare 'plat_late_platform_setup' handler in their platform
files, to override the default weakly defined handler.
Change-Id: Ibc97a2e5a24608ddea856d0bd543a9d5876f604c Signed-off-by: Dilan Lee <dilee@nvidia.com>
Varun Wadekar [Wed, 15 Nov 2017 23:48:51 +0000 (15:48 -0800)]
Tegra: spe: shared console for Tegra platforms
There are Tegra platforms which have limited UART ports and so
all the components have to share the console. The SPE helps out
by collecting all the logs in such cases and prints them on the
shared UART port.
This patch adds a driver to communicate with the SPE driver, which
in turn provides the console.
Varun Wadekar [Wed, 15 Nov 2017 23:46:38 +0000 (15:46 -0800)]
Tegra: console driver compilation from platform makefiles
This patch includes the console driver from individual platform
makefiles and removes it from tegra_common.mk. This allows future
platforms to include consoles of their choice.
Varun Wadekar [Wed, 8 Nov 2017 22:03:16 +0000 (14:03 -0800)]
Tegra: smmu: change exit criteria for context size calculation
Tegra SoCs currently do not have a SMMU register at address 0xFFFFFFFF.
This patch changes the search criteria, to look for this marker, to
calculate the size of the saved context.
Steven Kao [Tue, 14 Nov 2017 10:52:05 +0000 (18:52 +0800)]
Tegra: memctrl_v2: platform handler for TZDRAM setup
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform custom steps during TZDRAM setup.
Change-Id: Iee094d6ca189c6dd24f1147003c33c99ff3a953b Signed-off-by: Steven Kao <skao@nvidia.com>
Varun Wadekar [Fri, 10 Nov 2017 18:26:57 +0000 (10:26 -0800)]
Tegra186: save system suspend entry marker to TZDRAM
This patch adds support to save the system suspend entry and exit
markers to TZDRAM to help the trampoline code decide if the current
warmboot is actually an exit from System Suspend.
The Tegra186 platform handler sets the system suspend entry marker
before entering SC7 state and the trampoline flips the state back to
system resume, on exiting SC7.
Varun Wadekar [Wed, 8 Nov 2017 22:45:08 +0000 (14:45 -0800)]
Tegra186: helper functions for CPU rst handler and SMMU ctx offset
This patch adds a helper function to get the SMMU context's offset
and uses another helper function to get the CPU trampoline offset.
These helper functions are used by the System Suspend entry sequence
to save the SMMU context and CPU reset handler to TZDRAM.
Varun Wadekar [Wed, 23 Aug 2017 17:19:25 +0000 (10:19 -0700)]
Tegra: bpmp: return error if BPMP init fails
This patch returns error if BPMP initialization fails. The platform
code marks the cluster as "runnning" since we wont be able to get
it into the low power state without BPMP.
Varun Wadekar [Mon, 30 Oct 2017 21:35:17 +0000 (14:35 -0700)]
Tegra: memctrl_v2: platform handler for TZDRAM settings
The Tegra memctrl driver sets up the TZDRAM fence during boot and
system suspend exit. This patch provides individual platforms with
handlers to perform platform specific steps, e.g. enable encryption,
save base/size to secure scratch registers.
Varun Wadekar [Tue, 17 Oct 2017 17:29:24 +0000 (10:29 -0700)]
Tegra186: sanity check target cluster during core power on
This patch sanity checks the target cluster value, during core power on,
by comparing it against the maximum number of clusters supported by the
platform.
Tegra: bpmp_ipc: IPC driver to communicate with BPMP firmware
This patch adds the driver to communicate with the BPMP firmware on Tegra
SoCs, starting Tegra186. BPMP firmware is responsible for clock enable/
disable requests, module resets among other things.
MRQ is short for Message ReQuest. This is the general purpose, multi channel
messaging protocol that is widely used to communicate with BPMP. This is further
divided into a common high level protocol and a peer-specific low level protocol.
The higher level protocol specifies the peer identification, channel definition
and allocation, message structure, message semantics and message dispatch process
whereas the lower level protocol defines actual message transfer implementation
details. Currently, BPMP supports two lower level protocols - Token Mail Operations
(TMO), IVC Mail Operations (IMO).
This driver implements the IMO protocol. IMO is implemented using the IVC (Inter-VM
Communication) protocol which is a lockless, shared memory messaging queue management
protocol.
The IVC peer is expected to perform the following as part of establishing a connection
with BPMP.
1. Initialize the channels with tegra_ivc_init() or its equivalent.
2. Reset the channel with tegra_ivc_channel_reset. The peer should also ensure that
BPMP is notified via the doorbell.
3. Poll until the channel connection is established [tegra_ivc_channel_notified() return
0]. Interrupt BPMP with doorbell each time after tegra_ivc_channel_notified() return
non zero.
The IPC driver currently supports reseting the GPCDMAand XUSB_PADCTL hardware blocks. In
future, more hardware blocks would be supported.
Tegra: memctrl_v2: pack TZDRAM base to RSVD55_SCRATCH
This patch saves the TZDRAM_BASE value to secure RSVD55
scratch register. The warmboot code uses this register to
restore the settings on exiting System Suspend.
projects / arm-tf.git / log