Trusty requires dynamic translation tables support, so the makefile of
Trusty itself should request it. Not doing so causes platforms such as
FVP to fail to build with Trusty. Other platforms like Tegra still build
because they use dynamic translation tables by default.
Change-Id: Id67d3b9e1f7d0547fa81e81cefa3faf1e0e6f876 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
drivers: generic_delay_timer: Assert presence of Generic Timer
The Generic Timer is an optional extension to an ARMv7-A implementation.
The generic delay timer can be used from any architecture supported by
the Trusted Firmware. In ARMv7 it is needed to check that this feature
is present. In ARMv8 it is always present.
Change-Id: Ib7e8ec13ffbb2f64445d4ee48ed00f26e34b79b7 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Tegra: Enable irq as wake-up event for cpu_standby
As per ARM ARM D1.17.2, any physical IRQ interrupt received by the PE
will be treated as a wake-up event, if SCR_EL3.IRQ is set to '1',
irrespective of the value of the PSTATE.I bit value.
This patch programs the SCR_EL3.IRQ bit before entering CPU standby
state, to allow an IRQ to wake the PE. On waking up, the previous
SCR_EL3 value is restored.
Anthony Zhou [Mon, 2 Apr 2018 11:34:59 +0000 (19:34 +0800)]
Tegra: remove unused libc files from makefile
This patch redefines the variable LIBC_SRCS for Tegra platforms,
to remove unused libc files from the list. This patch is a building
block to eventually use other libc implementations in the future.
Change-Id: Iccde5a75f5e2d6f4e2dbc6274beb423b80e846fd Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar [Thu, 31 Jan 2019 17:22:30 +0000 (09:22 -0800)]
Introduce build option to override libc
This patch introduces a build option 'OVERRIDE_LIBC' that platforms
can set to override libc from the BL image. The default value is '0'
to keep the library.
Thomas Abraham [Fri, 7 Dec 2018 04:28:50 +0000 (09:58 +0530)]
sgi/sgm: add a second maintainer for Arm's SGI and SGM platforms
Add a second maintainer for Arm's SGI and SGM platform support in
trusted firmware to handle the review and maintenance of
existing and upcoming platforms.
Change-Id: Ie7fa8da280d9351f7543122fb261d6ac6c7e15ad Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Soby Mathew [Thu, 17 Jan 2019 14:57:54 +0000 (14:57 +0000)]
GICv3: Allow probe for fewer GICR interfaces than exposed by the frame
Previously the GICv3 redistributor probe function
(gicv3_rdistif_base_addrs_probe()) asserted that the number of
per-CPU redistributor interfaces expected to be probed by the
platform is equal to the number exported by the redistributor
frame. This is a problem in case the number of CPUs in the
platform is less than the number of redistributor interfaces
in the frame. Hence this patch removes the assertion check
and allows probe for fewer redistributor interfaces as required
by the platform.
Many parts of the code were duplicating symbols that are defined in
include/common/bl_common.h. It is better to only use the definitions in
this header.
As all the symbols refer to virtual addresses, they have to be
uintptr_t, not unsigned long. This has also been fixed in bl_common.h.
Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit adds SDHost driver for RaspberryPi3. SDHost driver uses the
GPIO driver to connect the SDCard and SDHost. By using this driver it is
able to read/write raw blocks on SDCard.
Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Varun Wadekar [Mon, 12 Mar 2018 22:11:55 +0000 (15:11 -0700)]
Tegra: restrict non-secure PMC accesses
Platforms that do not support bpmp firmware, do not need access
to the PMC block from outside of the CPU complex. The agents
running on the CPU can always access the PMC through the EL3
exception space.
This patch restricts non-secure world access to the PMC block on
such platforms.
Krishna Reddy [Thu, 7 Dec 2017 21:52:39 +0000 (13:52 -0800)]
Tegra186: memctrl: disable stream id writes for MC clients
As per the latest recommendations from the hardware team, write access
needs to be disabled for APE, BPMP, NvDec and SCE clients. This patch
disables stream id register writes for these MC clients to implement
those recommendations.
Tegra: bpmp: mark device "not present" on boot timeout
This patch updates the state machine to "not present" if the bpmp
firmware is not found in the system during boot. The suspend
handler also checks now if the interface exists, before updating
the internal state machine.
Tegra210: toggle ring oscillator across cluster idle
This patch toggles the ring oscillator state across cluster idle
as DFLL loses its state. We dont want garbage values being written
to the pmic when we enter cluster idle state, so enable "open loop"
when we enter CC6 and restore the state to "closed loop" on exit.
Tegra210: suspend/resume bpmp interface across System Suspend
The BPMP firmware takes some time to initialise its state on exiting
System Suspend state. The CPU needs to synchronize with the BPMP during
this process to avoid any race conditions. This patch suspends and resumes
the BPMP interface across a System Suspend cycle, to fix this race.
This patch adds suspend and resume handlers for the BPMP
interface. Mark the interface as "suspended" before entering
System Suspend and verify that BPMP is alive on exit.
Stephen Wolfe [Thu, 29 Mar 2018 19:32:08 +0000 (12:32 -0700)]
spd: trusty: pass max affinity level to Trusty
During System Suspend, the entire system loses its state. To allow Trusty
to save/restore its context and allow its TAs to participate in the suspend
process, it needs to look at the max affinity level being suspended. This
patch passes the max affinity level to Trusty to enable to do so.
Varun Wadekar [Mon, 19 Mar 2018 22:19:28 +0000 (15:19 -0700)]
Tegra210: skip past sc7entry-fw signature header
This patch skips past the signature header added to the sc7entry-fw
binary by the previous level bootloader. Currently, the size of
the header is 1KB, so adjust the start address and the binary size
at the time of copy.
This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.
Varun Wadekar [Mon, 5 Mar 2018 18:19:37 +0000 (10:19 -0800)]
Tegra210: power off all DMA masters before System Suspend entry
This patch puts all the DMA masters in reset before starting the System
Suspend sequence. This helps us make sure that there are no rogue agents
in the system trying to over-write the SC7 Entry Firmware with their own.
Mihir Joshi [Thu, 1 Mar 2018 22:36:24 +0000 (14:36 -0800)]
spd: tlkd: remove unwanted assert on System Suspend entry
c_rt_ctx is used to store current SP before the system goes
into suspend. The assert for its value being zero is not
really necessary as the value gets over-written eventually.
This patch removes assert(tlk_ctx->c_rt_ctx == 0) from the
System Suspend path, as a result.
Varun Wadekar [Tue, 27 Feb 2018 22:33:57 +0000 (14:33 -0800)]
Tegra: support for System Suspend using sc7entry-fw binary
This patch adds support to enter System Suspend on Tegra210 platforms
without the traditional BPMP firmware. The BPMP firmware will no longer
be supported on Tegra210 platforms and its functionality will be
divided across the CPU and sc7entry-fw.
The sc7entry-fw takes care of performing the hardware sequence required
to enter System Suspend (SC7 power state) from the COP. The CPU is required
to load this firmware to the internal RAM of the COP and start the sequence.
The CPU also make sure that the COP is off after cold boot and is only
powered on when we want to start the actual System Suspend sequence.
The previous bootloader loads the firmware to TZDRAM and passes its base and
size as part of the boot parameters. The EL3 layer is supposed to sanitize
the parameters before touching the firmware blob.
To assist the warmboot code with the PMIC discovery, EL3 is also supposed to
program PMC's scratch register #210, with appropriate values. Without these
settings the warmboot code wont be able to get the device out of System
Suspend.
Varun Wadekar [Wed, 14 Feb 2018 04:31:12 +0000 (20:31 -0800)]
Tegra210: support for cluster idle from the CPU
This patch adds support to enter/exit to/from cluster idle power
state on Tegra210 platforms that do not load BPMP firmware.
The CPU initates the cluster idle sequence on the last standing
CPU, by following these steps:
Entry
-----
* stop other CPUs from waking up
* program the PWM pinmux to tristate for OVR PMIC
* program the flow controller to enter CC6 state
* skip L1 $ flush during cluster power down, as L2 $ is inclusive
of L1 $ on Cortex-A57 CPUs
Exit
----
* program the PWM pinmux to un-tristate for OVR PMIC
* allow other CPUs to wake up
This patch also makes sure that cluster idle state entry is not
enabled until CL-DVFS is ready.
Steven Kao [Fri, 9 Feb 2018 12:50:02 +0000 (20:50 +0800)]
Tegra: platform dependent address space sizes
This patch moves the PLAT_PHY_ADDR_SPACE_SIZE & PLAT_VIRT_ADDR_SPACE
macros to tegra_def.h, to define the virtual/physical address space
size on the platform.
Change-Id: I1c5d264c7ffc1af0e7b14cc16ae2c0416efc76f6 Signed-off-by: Steven Kao <skao@nvidia.com>
Varun Wadekar [Tue, 23 Jan 2018 22:38:51 +0000 (14:38 -0800)]
Tegra: organize memory/mmio apertures to decrease memmap latency
This patch organizes the memory and mmio maps linearly, to make the
mmap_add_region process faster. The microsecond timer has been moved
to individual platforms instead of making it a common step, as it
further speeds up the memory map creation process.
Varun Wadekar [Thu, 3 Jan 2019 01:53:15 +0000 (17:53 -0800)]
Tegra210: Enable WDT_CPU interrupt for FIQ Debugger
This patch enables the watchdog timer's interrupt as an FIQ
interrupt to the CPU. The interrupt generated by the watchdog
is connected to the flow controller for power management reasons,
and needs to be routed to the GICD for it to reach the CPU.
Varun Wadekar [Wed, 14 Feb 2018 16:38:27 +0000 (08:38 -0800)]
Tegra: flowctrl: helper functions to assist with cluster power states
This patch adds helper functions to help platforms with cluster state entry
and exit decisions.
* tegra_fc_ccplex_pgexit_lock(): lock CPU power ungate
* tegra_fc_ccplex_pgexit_unlock(): unlock CPU power ungate
* tegra_fc_is_ccx_allowed(): CCx state entry allowed on this CPU?
Varun Wadekar [Wed, 14 Feb 2018 04:08:24 +0000 (20:08 -0800)]
Tegra: bpmp: remove bpmp init failed error print
This patch removes the error print displayed when bpmp init
fails. On platforms that do not load the bpmp firmware, this
print is seen on every cluster idle and powerdown request,
cluttering the logs.
Varun Wadekar [Fri, 26 Jan 2018 18:33:42 +0000 (10:33 -0800)]
Tegra: fiq_glue: support to handle LEGACY_FIQ PPIs for Tegra SoCs
This patch adds support to handle secure PPIs for Tegra watchdog timers. This
functionality is currently protected by the ENABLE_WDT_LEGACY_FIQ_HANDLING
configuration variable and is only enabled for Tegra210 platforms, for now.
Varun Wadekar [Fri, 26 Jan 2018 18:05:02 +0000 (10:05 -0800)]
Tegra: flowctrl: support to enable/disable WDT's legacy FIQ routing
On earlier Tegra platforms, e.g. Tegra210, the watchdog timer's FIQ interrupt
is not direclty wired to the GICD. It goes to the flow controller instead, for
power state management. But the flow controller can route the FIQ to the GICD,
as a PPI, which can then get routed to the target CPU.
This patch adds routines to enable/disable routing the legacy FIQ used by
the watchdog timers, to the GICD.
Jeetesh Burman [Mon, 22 Jan 2018 10:10:08 +0000 (15:40 +0530)]
Tegra: SiP: set GPU in reset after vpr resize
Whenever the VPR memory is resized, the GPU is put into reset first
and then the new VPR parameters are programmed to the memory controller
block. There exists a scenario, where the GPU might be out before we
program the new VPR parameters. This means, the GPU would still be
using older settings and leak secrets.
This patch puts the GPU back into reset, if it is out of reset after
resizing VPR, to mitigate this hole.
steven kao [Wed, 3 Jan 2018 03:07:00 +0000 (19:07 -0800)]
Tegra: bpmp_ipc: support to enable/disable module clocks
This patch adds support to the bpmp_ipc driver to allow clients to
enable/disable clocks to hardware blocks. Currently, the API only
supports SE devices.
Change-Id: I9a361e380c0bcda59f5a92ca51c86a46555b2e90 Signed-off-by: steven kao <skao@nvidia.com>
Varun Wadekar [Tue, 2 Jan 2018 22:10:18 +0000 (14:10 -0800)]
Tegra: fix offset used to dump GICD registers from crash handler
The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.
Varun Wadekar [Thu, 28 Dec 2017 02:10:12 +0000 (18:10 -0800)]
Tegra: default platform handler for the CPU_STANDBY state
This patch adds a default implementation for the platform specific
CPU standby power handler. Tegra SoCs can override this handler
with their own implementations.
Sathees Balya [Fri, 25 Jan 2019 11:36:01 +0000 (11:36 +0000)]
lib/xlat_tables: Add support for ARMv8.4-TTST
ARMv8.4-TTST (Small Translation tables) relaxes the lower limit on the
size of translation tables by increasing the maximum permitted value
of the T1SZ and T0SZ fields in TCR_EL1, TCR_EL2, TCR_EL3, VTCR_EL2 and
VSTCR_EL2.
This feature is supported in AArch64 state only.
This patch adds support for this feature to both versions of the
translation tables library. It also removes the static build time
checks for virtual address space size checks to runtime assertions.
Paul Beesley [Mon, 21 Jan 2019 12:06:24 +0000 (12:06 +0000)]
doc: Link coding guidelines to user guide
Adds a link from user-guide.rst to coding-guidelines.rst and merges
the information about using checkpatch from both files into the user
guide document.
Change-Id: Iffbb4225836a042d20024faf28b8bdd6b2c4043e Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley [Thu, 17 Jan 2019 15:44:37 +0000 (15:44 +0000)]
doc: Add Coding Guidelines document
This content has been imported and adapted from the TF GitHub wiki
article 'ARM-Trusted-Firmware-Coding-Guidelines'.
The aim is to increase the visibility of the coding guidelines by
including them as part of the documentation that is within the TF
repository.
Additionally, the documentation can then be linked to by other
documents in the docs/ directory without worrying about broken links
to, for example, the external wiki.
Change-Id: I9d8cd6b5117b707c1a113baeba7fc5e1b4bf33bc Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Andre Przywara [Tue, 29 Jan 2019 09:25:14 +0000 (09:25 +0000)]
tools/fiptool: Fix UUID parsing in blob handling
Commit 033648652f ("Make TF UUID RFC 4122 compliant") changed the scanf
parsing string to handle endianness correctly.
However that changed the number of items sscanf handles, without
adjusting the sanity check just below.
Increase the expected return value from 11 to 16 to let fiptool handle
UUIDs given as blob parameters correctly again.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Method cpld_reset_cpu of bl31 is called from the Linux kernel and uses
GPIO6, GPIO2 pins as SPI bus lines to control the CPLD device. But in the
kernel GPIO6_8 pin are initialized to work in interrupt mode instead of
the input/output mode. This leads to the fact that the SPI bus becomes
non-functional. In this patch we switch the GPIO6_8 pin back to the
input-output mode.
Signed-off-by: Sergii Boryshchenko <sergii.boryshchenko@globallogic.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Tue, 29 Jan 2019 05:06:08 +0000 (06:06 +0100)]
Revert "rcar_gen3: plat: Enable programmable CPU reset address"
This reverts commit d48536e2f92d47ebb92cf12b35133c3be2d0e459,
which misbehaves on R-Car H3 ES2.0. Until the reason for that
misbehavior is understood, revert the commit.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Anson Huang [Thu, 24 Jan 2019 08:50:02 +0000 (16:50 +0800)]
imx: power optimization for i.mx8qx
Current implementation of i.MX8QX power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.
To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.
If resources are powered off for suspend, they should be restored
properly after system resume.
Anson Huang [Thu, 24 Jan 2019 08:09:52 +0000 (16:09 +0800)]
imx: power optimization for i.mx8qm
Current implementation of i.MX8QM power management related
features does NOT optimize power number, all system resources
like CCI, DDR, and A cluster etc. are kept in STBY mode (powered
ON) when system suspend or CPU hotplug.
To lower the power number, OFF mode should be adopted for those
system resources whenever they can be OFF, A cluster will be OFF
if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF
if system suspend, IRQ steer can be OFF if the wakeup source is
belonged to system controller partition, so wakeup source runtime
check is used to determine if IRQ steer can be OFF before system
suspend.
If resources are powered off for suspend, they should be restored
properly after system resume.
After the removal of deprecated interfaces in TF 2.0 the migration to
the new GIC driver interfaces was done incorrectly in rk3328 and rk3368: 2d6f1f01b141 ("rockchip: Migrate to new interfaces").
In the GICv2 driver it is mandated that all interrupts are Group 0
interrupts. This patch simply moves all Group 1 interrupts to Group 0.
Change-Id: I224c0135603eb5b81bd512976361500c0d129a91 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
projects / arm-tf.git / log