John Powell [Fri, 20 Mar 2020 19:21:05 +0000 (14:21 -0500)]
Fix MISRA C issues in BL1/BL2/BL31
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.
Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a Signed-off-by: John Powell <john.powell@arm.com>
Andrei Warkentin [Thu, 12 Mar 2020 05:11:06 +0000 (22:11 -0700)]
rpi: Implement PSCI CPU_OFF
We simulate the PSCI CPU_OFF operation by reseting the core via RMR.
For secondaries, that already puts them in the holding pen waiting for a
"warm boot" request as part of PSCI CPU_ON. For the BSP, we have to add
logic to distinguish a regular boot from a CPU_OFF state, where, like the
secondaries, the BSP needs to wait foor a "warm boot" request as part
of CPU_ON.
Testing done:
- ACS suite now passes more tests (since it repeatedly
calls code on secondaries via CPU_ON).
- Linux testing including offlining/onlineing CPU0, e.g.
"echo 0 > /sys/devices/system/cpu/cpu0/online".
Change-Id: Id0ae11a0ee0721b20fa2578b54dadc72dcbd69e0 Link: https://developer.trustedfirmware.org/T686 Signed-off-by: Andrei Warkentin <andrey.warkentin@gmail.com>
[Andre: adapt to unified plat_helpers.S, smaller fixes] Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Sat, 21 Mar 2020 11:22:13 +0000 (11:22 +0000)]
rpi: rpi3_pwr_domain_on(): Use MMIO accessor
When writing to arbitrary locations in memory using a constructed
pointer, there is no guarantee that the compiler does not optimise away
the access, since it cannot detect any dependency.
One typical solution is to use the "volatile" keyword, but using MMIO
accessors in usually the better answer, to avoid torn writes.
Replace the usage of an array with such an MMIO accessor function in
rpi3_pwr_domain_on(), to make sure the write is really happening.
Change-Id: Ia18163c95e92f1557471089fd18abc6dc7fee0c7 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Thu, 12 Mar 2020 14:20:04 +0000 (14:20 +0000)]
rpi: move plat_helpers.S to common
The plat_helpers.S file was almost identical between its RPi3 and RPi4
versions. Unify the two files, moving it into the common/ directory.
This adds a plat_rpi_get_model() function, which can be used to trigger
RPi4 specific action, detected at runtime. We use that to do the RPi4
specific L2 cache initialisation.
Change-Id: I2295704fd6dde7c76fe83b6d98c7bf998d4bf074 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Masahiro Yamada [Thu, 26 Mar 2020 04:18:48 +0000 (13:18 +0900)]
uniphier: support read-only xlat tables
BL2 for this platform uses mmap_add_dynamic_region(), but BL31 and
BL32 (TSP) only use static mapping. So, BL31 and BL32 can make the
tables read-only after enabling MMU.
Enable MTE support by adding memory tag option in Makefile
This option is available only when ARMv8.5-MemTag is implemented
MTE options are added in latest clang and armclang compiler which
support below options:
for clang <version 11.0.0>
1. -march=arm8.5-a+memtag
2. -fsanitize=memtag
for armclang <version 6.12>
1. -march=arm8.5-a+memtag
2. -mmemtag-stack
Set the option SUPPORT_STACK_MEMTAG=yes to enable memory stack tagging.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I4e0bbde4e9769ce03ead6f550158e22f32c1c413
Add support to pass the nt_fw_config DTB to OP-TEE.
At the moment, OP-TEE has no support to receive a DTB in Secure Memory
so it cannot receive TOS_FW_CONFIG_ID as it is supposed to happen on
any BL32 image. Instead, when OP-TEE is enable as BL32 payload,
NT_FW_CONFIG_ID is passed.
This MUST be reverted as soon as OP-TEE has support for receiving
DTBs from Secure Memory.
Change-Id: I9a873f42e94f2f99a60b638333e7afba1505aec9 Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Ahmad Fatoum [Tue, 25 Feb 2020 10:25:08 +0000 (11:25 +0100)]
Makefile: don't use $(CC) before value is explicit set
Unless specified in the environment, $(CC) expands to some generic
host C compiler like cc or c99. We set our own value for $(CC), but
only few lines later.
Move the first use of the $(CC) variable behind the definition to
correct this.
Change-Id: I45344e063d21ddfe22b7ad77954e85c1c46087bd Fixes: 1684b8733 ("Use clang assembler when clang compiler is used") Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Masahiro Yamada [Wed, 25 Mar 2020 08:50:39 +0000 (17:50 +0900)]
plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS
-D is a preprocessor flag that defines a macro. So, adding it to
BL*_CPPFLAGS makes more sense. You can reference it not only from
.c files but also from .S files.
Masahiro Yamada [Thu, 26 Mar 2020 04:18:48 +0000 (13:18 +0900)]
xlat_tables_v2: add enable_mmu()
enable_mmu_* has a different function name, so it is not handy in the
shared code. enable_mmu() calls an appropriate one depending on the
exception level.
Masahiro Yamada [Thu, 26 Mar 2020 04:18:48 +0000 (13:18 +0900)]
Add get_current_el_maybe_constant()
There are some cases where we want to run EL-dependent code in the
shared code.
We could use #ifdef, but it leaves slight possibility where we do not
know the exception level at the build-time (e.g. library code).
The counter approach is to use get_current_el(), but it is run-time
detection, so all EL code is linked, some of which might be unneeded.
This commit adds get_current_el_maybe_constant(). This is a static
inline function that returns a constant value if we know the exception
level at build-time. This is mostly the case.
if (get_current_el_maybe_constant() == 1) {
/* do something for EL1 */
} else if (get_current_el_maybe_constant() == 3) {
/* do something for EL3 */
}
If get_current_el_maybe_constant() is build-time constant, the compiler
will optimize out the unreachable code.
If such code is included from the library code, it is not built-time
constant. In this case, it falls back to get_current_el(), so it still
works.
Masahiro Yamada [Thu, 26 Mar 2020 04:18:48 +0000 (13:18 +0900)]
Build: define IMAGE_AT_EL1 or IMAGE_AT_EL3 globally for C files
The build system defines the IMAGE_BL* macro when compiling each image.
This is useful to distinguish which image the current file is being
built for by using #if defined(IMAGE_BL2) or #if defined(IMAGE_BL31),
or whatever.
There are some cases where we are more interested in which exception
level the current file is being built for.
include/lib/cpus/{aarch32,aarch64}/cpu_macros.S defines IMAGE_AT_EL3,
but we do not have it globally.
Pass IMAGE_AT_EL1 or IMAGE_AT_EL3 to BL*_CFLAGS so that it is available
from all C code.
The library code (libc.a, libmbedtls.a, etc.) is exceptional cases,
where the code can be shared between BL images.
Other than that, we know the exception level at the build time, and
this macro will be useful in the shared code.
Olivier Deprez [Mon, 30 Mar 2020 15:27:32 +0000 (15:27 +0000)]
Merge changes from topic "ddr_map" into integration
* changes:
stm32mp1: use stm32mp_get_ddr_ns_size() function
stm32mp1: set XN attribute for some areas in BL2
stm32mp1: dynamically map DDR later and non-cacheable during its test
stm32mp1: add a function to get non-secure DDR size
Alexei Fedorov [Mon, 23 Mar 2020 18:45:17 +0000 (18:45 +0000)]
TF-A GICv3 driver: Introduce makefile
This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.
NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.
Manish Pandey [Fri, 27 Mar 2020 17:54:21 +0000 (17:54 +0000)]
Merge changes from topic "os/bl31-fpga-port" into integration
* changes:
plat/arm/board/arm_fpga: Compile with additional CPU libraries
plat/arm/board/arm_fpga: Enable position-independent execution
plat/arm/board/arm_fpga: Enable port for alternative cluster configurations
plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller
plat/arm/board/arm_fpga: Initialize the System Counter
plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images
plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image
Zelalem [Thu, 26 Mar 2020 21:15:34 +0000 (16:15 -0500)]
Flush dcache when storing timestamp
On DynamIQ CPU FVPs, stats test cases are failing when
hardware-assisted coherency is enabled due to a corrupt
timestamp value. Investigation of the issue indicates that
on these models the timestamp value is stored in cache
instead of memory. This patch flushes the dcache when the
timestamp is stored to make sure it is stored in memory.
Oliver Swede [Wed, 15 Jan 2020 10:20:09 +0000 (10:20 +0000)]
plat/arm/board/arm_fpga: Compile with additional CPU libraries
This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.
BL31 behaves differently depending on whether or not the CPUs in the
system use cache coherency, and as a result any CPU libraries that are
compiled together must serve processors that are consistent in this
regard.
This compiles a different set of CPU libraries depending on whether or
not the HW_ASSISTED_COHERENCY is enabled at build-time to indicate the
CPUs support hardware-level support for cache coherency. This build
flag is used in the makefile in the same way as the Arm FVP port.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I18300b4443176b89767015e3688c0f315a91c27e
This allows the BL31 port to run with position-independent execution
enabled so that it can be ran from any address in the system.
This increases the flexibility of the image, allowing it to be ran from
other locations rather than only its hardcoded absolute address
(currently set to the typical DRAM base of 2GB). This may be useful for
future images that describe system configurations with other memory
layouts (e.g. where SRAM is included).
It does this by setting ENABLE_PIE=1 and changing the absolute
address to 0. The load address of bl31.bin can then be specified by
the -l [load address] argument in the fpga-run command (additionally,
this address is required by any preceding payloads that specify the
start address. For ELF payloads this is usually extracted automatically
by reading the entrypoint address in the header, however bl31.bin is a
different file format so has this additional dependency).
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Idd74787796ab0cf605fe2701163d9c4b3223a143
Oliver Swede [Mon, 16 Dec 2019 14:08:27 +0000 (14:08 +0000)]
plat/arm/board/arm_fpga: Enable port for alternative cluster configurations
This change is part of the goal of enabling the port to be compatible
with multiple FPGA images.
The BL31 port that is uploaded as a payload to the FPGA with an image
should cater for a wide variety of system configurations. This patch
makes the necessary changes to enable it to function with images whose
cluster configurations may be larger (either by utilizing more
clusters, more CPUs per cluster, more threads in each CPU, or a
combination) than the initial image being used for testing.
As part of this, the hard-coded values that configure the size of the
array describing the topology of the power domain tree are increased
to max. 8 clusters, max. 8 cores per cluster & max 4 threads per core.
This ensures the port works with cluster configurations up to these
sizes. When there are too many entries for the number of available PEs,
e.g. if there is a variable number of CPUs between clusters, then there
will be empty entries in the array. This is permitted and the PSCI
library will still function as expected. While this increases its size,
this shouldn't be an issue in the context of the size of BL31, and is
worth the trade-off for the extra compatibility.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
Oliver Swede [Tue, 3 Dec 2019 14:08:21 +0000 (14:08 +0000)]
plat/arm/board/arm_fpga: Initialize the Generic Interrupt Controller
This initializes the GIC using the Arm GIC drivers in TF-A.
The initial FPGA image uses a GIC600 implementation, and so that its
power controller is enabled, this platform port calls the corresponding
implementation-specific routines.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I88d5a073eead4b653b1ca73273182cd98a95e4c5
Oliver Swede [Mon, 2 Dec 2019 13:33:40 +0000 (13:33 +0000)]
plat/arm/board/arm_fpga: Initialize the System Counter
This sets the frequency of the system counter so that the Delay Timer
driver programs the correct value to CNTCRL. This value depends on
the FPGA image being used, and is 10MHz for the initial test image.
Once configured, the BL31 platform setup sequence then enables the
system counter.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
Oliver Swede [Mon, 2 Dec 2019 13:21:52 +0000 (13:21 +0000)]
plat/arm/board/arm_fpga: Add PSCI implementation for FPGA images
This adds a basic PSCI implementation allow secondary CPUs to be
released from an initial state and continue through to the warm boot
entrypoint.
Each secondary CPU is kept in a holding pen, whereby it polls the value
representing its hold state, by reading this from an array that acts as
a table for all the PEs. The hold states are initially set to 0 for all
cores to indicate that the executing core should continue polling.
To prevent the secondary CPUs from interfering with the platform's
initialization, they are only updated by the primary CPU once the cold
boot sequence has completed and fpga_pwr_domain_on(mpidr) is called.
The polling target CPU will then read 1 (which indicates that it should
branch to the warm reset entrypoint) and then jump to that address
rather than continue polling.
In addition to the initial polling behaviour of the secondary CPUs
before their warm boot reset sequence, they are also placed in a
low-power wfe() state at the end of each poll; accordingly, the PSCI
fpga_pwr_domain_on(mpidr) function also signals an event to all cores
(after updating the target CPU's hold entry) to wake them from this
state, allowing any secondary CPUs that are still polling to check
their hold state again.
This method is in accordance with both the PSCI and Linux kernel
recommendations, as the lessened overhead reduces the energy
consumption associated with the busy-loop.
The table of hold entries is implemented by a global array as shared SRAM
(which is used by other platforms in similar implementations) is not
available on the FPGA images.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I65cfd1892f8be1dfcb285f0e1e94e7a9870cdf5a
Oliver Swede [Mon, 11 Nov 2019 11:32:32 +0000 (11:32 +0000)]
plat/arm/board/arm_fpga: Use preloaded BL33 alternative boot flow
This makes use of the PRELOADED_BL33_BASE flag to indicate to BL31 that
the BL33 payload (kernel) has already been loaded and resides in memory;
BL31 will then jump to the non-secure address.
For this port the BL33 payload is the Linux kernel, and in accordance
with the pre-kernel setup requirements (as specified in the `Booting
AArch64 Linux' documentation:
https://www.kernel.org/doc/Documentation/arm64/booting.txt),
this change also sets up the primary CPU's registers x0-x3 so they are
the expected values, which includes the address of the DTB at x0.
An external linker script is currently required to combine BL31, the
BL33 payload, and any other software images to create an ELF file that
can be uploaded to the FPGA board along with the bit file. It therefore
has dependencies on the value of PRELOADED_BL33_BASE (kernel base) and
the DTB base (plus any other relevant base addresses used to
distinguish the different ELF sections), both of which are set in this
patch.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: If7ae8ee82d1e09fb05f553f6077ae13680dbf66b
Oliver Swede [Mon, 11 Nov 2019 11:11:06 +0000 (11:11 +0000)]
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image
This adds the minimal functions and definitions to create a basic
BL31 port for an initial FPGA image, in order for the port to be
uploaded to one the FPGA boards operated by an internal group within
Arm, such that BL31 runs as a payload for an image.
Future changes will enable the port for a wide range of system
configurations running on the FPGA boards to ensure compatibility with
multiple FPGA images.
It is expected that this will replace the FPGA fork of the Linux kernel
bootwrapper by performing similar secure-world initialization and setup
through the use of drivers and other well-established methods, before
passing control to the kernel, which will act as the BL33 payload and
run in EL2NS.
This change introduces a basic, loadable port with the console
initialized by setting the baud rate and base address of the UART as
configured by the Zeus image.
It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this.
Signed-off-by: Oliver Swede <oli.swede@arm.com>
Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
Yann Gautier [Fri, 10 Jan 2020 17:18:59 +0000 (18:18 +0100)]
stm32mp1: dynamically map DDR later and non-cacheable during its test
A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.
The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.
PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.
BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.
Yann Gautier [Wed, 26 Feb 2020 12:39:44 +0000 (13:39 +0100)]
stm32mp1: add a function to get non-secure DDR size
This function gets the DDR size from DT, and withdraws (if defined) the
sizes of secure DDR and shared memory areas.
This function also checks DT values fits the default DDR range.
This non-secure memory is available for BL33 and non-secure OS.
Fixed below 'tautological-constant-compare' error when building the source
code with latest clang compiler <clang version 11.0.0>.
plat/common/plat_psci_common.c:36:2:
error: converting the result of '<<' to a boolean always evaluates
to true [-Werror,-Wtautological-constant-compare]
PMF_STORE_ENABLE)
^
include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE'
PMF_STORE_ENABLE (1 << 0)
This error is observed beacuse of CASSERT placed in
"PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff:
CASSERT(_flags, select_proper_config);
where _flags = PMF_STORE_ENABLE (1 << 0) which always results true.
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021
Varun Wadekar [Sun, 22 Mar 2020 22:58:02 +0000 (15:58 -0700)]
Tegra194: se: increase max. operation timeout to 1 second
This patch increases the maximum timeout value for SE operation
completion to 1 second. This takes care of some corner cases where
an operation might take more time than the previous timeout value
of 100ms.
Olivier Deprez [Thu, 19 Mar 2020 08:27:11 +0000 (09:27 +0100)]
spmd: skip loading of secure partitions on pre-v8.4 platforms
When SPD=spmd and SPMD_SPM_AT_SEL2=0, that is SPMC sits at S-EL1
then there is no need for TF-A to load secure partitions individually.
In this configuration, SPMC handles secure partition loading at
S-EL1/EL0 levels.
Yann Gautier [Wed, 18 Mar 2020 13:50:50 +0000 (14:50 +0100)]
io: io_stm32image: correct possible NULL pointer dereference
This issue was found with cppcheck in our downstream code:
[drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]:
(warning) Either the condition 'buffer!=0U' is redundant or there is
possible null pointer dereference: local_buffer.
Yann Gautier [Wed, 18 Mar 2020 13:35:27 +0000 (14:35 +0100)]
plat/st: correctly check pwr-regulators node
This warning was issued by cppcheck in our downstream code:
[plat/st/common/stm32mp_dt.c:629] -> [plat/st/common/stm32mp_dt.c:634]:
(warning) Identical condition 'node<0', second condition is always false
The second test has to check variable pwr_regulators_node.
Yann Gautier [Wed, 11 Mar 2020 16:17:51 +0000 (17:17 +0100)]
plat/st: correct static analysis tool warning
Correct the following sparse warnings:
plat/st/common/stm32mp_dt.c:103:5: warning:
symbol 'fdt_get_node_parent_address_cells' was not declared.
Should it be static?
plat/st/common/stm32mp_dt.c:123:5: warning:
symbol 'fdt_get_node_parent_size_cells' was not declared.
Should it be static?
As those 2 functions are only used by assert(), put them under
ENABLE_ASSERTIONS flag.
Yann Gautier [Wed, 11 Mar 2020 16:16:49 +0000 (17:16 +0100)]
raw_nand: correct static analysis tool warning
Correct the following warning given by sparse tool:
include/drivers/raw_nand.h:158:3: warning:
symbol '__packed' was not declared. Should it be static?
Yann Gautier [Wed, 11 Mar 2020 16:09:21 +0000 (17:09 +0100)]
spi: stm32_qspi: correct static analysis issues
Sparse issue:
drivers/st/spi/stm32_qspi.c:445:5:
warning: symbol 'stm32_qspi_init' was not declared. Should it be static?
Cppcheck issue:
[drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]:
(style) Variable 'len' is reassigned a value before the old one has been
used.
[drivers/st/spi/stm32_qspi.c:178]:
(style) The scope of the variable 'timeout' can be reduced.
Igor Opaniuk [Mon, 23 Mar 2020 15:21:05 +0000 (17:21 +0200)]
plat: imx: imx8qx: provide debug uart num as build param
1. This removes hardcoded iomux/clk/addr configuration for debug uart,
provides possibility (as a workaround, till that information isn't
provided via DT) to set this configuration during compile time via
IMX_DEBUG_UART build flag.
Also for Colibri i.MX8QXP different pinmux configuration is applied
for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX.
2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35
doesn't make sense (since UART pinmux/clock configuration is applied
for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit
for i.MX8QM 98a69dfd4a("plat: imx: imx8qm: apply clk/pinmux
configuration for DEBUG_CONSOLE")).
Usage:
$ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760
Manish Pandey [Mon, 23 Mar 2020 15:24:02 +0000 (15:24 +0000)]
Merge changes from topic "tegra-downstream-03192020" into integration
* changes:
Tegra194: move cluster and CPU counter to header file.
Tegra: gicv2: initialize target masks
spd: tlkd: support new TLK SMCs for RPMB service
Tegra210: trigger CPU0 hotplug power on using FC
Tegra: memctrl: cleanup streamid override registers
Tegra: memctrl_v2: remove support to secure TZSRAM
Tegra: include platform headers from individual makefiles
Tegra210: rename ENABLE_WDT_LEGACY_FIQ_HANDLING macro
Tegra194: SiP function ID to read SMMU_PER registers
Tegra: memctrl: map video memory as uncached
Tegra: remove support for USE_COHERENT_MEM
Tegra: remove circular dependency with common_def.h
Tegra: include missing stdbool.h
Tegra: remove support for SEPARATE_CODE_AND_RODATA=0
Anthony Zhou [Mon, 11 Mar 2019 07:50:32 +0000 (15:50 +0800)]
Tegra194: move cluster and CPU counter to header file.
MISRA rules request that the cluster and CPU counter be unsigned
values and have a suffix 'U'. If the define located in the makefile,
this cannot be done.
This patch moves the PLATFORM_CLUSTER_COUNT and PLATFORM_MAX_CPUS_PER_CLUSTER
macros to tegra_def.h as a result.
Change-Id: I9ef0beb29485729de204b4ffbb5241b039690e5a Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
projects / arm-tf.git / log