Tegra186: mce: read MCE's firmware version on "real" platforms
This patch runs the MCE firmware's version check only if the underlying
platform has the capability to the run the firmware. MCE firmware is not
running on simulation platforms, identified by v0.3 or v0.6, read from the
Tegra Chip ID value.
Varun Wadekar [Thu, 2 Jun 2016 21:26:13 +0000 (14:26 -0700)]
Tegra186: implement plat_get_syscnt_freq2()
Commit f3d3b316f82faa88e42f3d09c97cd9e52ac92599 replaced
plat_get_syscnt_freq by plat_get_syscnt_freq2 on all the
upstream platforms. This patch modifies the Tegra186 code
which is not present usptream, yet.
Varun Wadekar [Mon, 23 May 2016 18:47:34 +0000 (11:47 -0700)]
Tegra186: handlers to get BL31 arguments from previous bootloader
This patch overrides the default handlers to get BL31 arguments from the
previous bootloader. The previous bootloader stores the pointer to the
arguments in PMC secure scratch register #53.
BL31 is the first component running on the CPU, as there isn't a previous
bootloader. We set the RESET_TO_BL31 flag to enable the path which assumes
that there are no input parameters passed by the previous bootloader.
Varun Wadekar [Wed, 1 Jun 2016 19:48:13 +0000 (12:48 -0700)]
Tegra186: delete 'Video Memory Carveout' handling
This patch removes duplicate code from the platform's SiP handler
routine for processing Video Memory Carveout region requests and
uses the common SiP handler instead.
This patch enables the configuration settings for the TZRAM
aperture by programming the base/size of the aperture and
restricting access to it. We allow only the CPU to read/write
by programming the access configuration registers to 0.
Uncore perfmon appears to the CPU as a set of uncore perfmon registers
which can be read and written using the ARI interface. The MCE code
sequence handles reads and writes to these registers by manipulating
the underlying T186 uncore hardware.
To access an uncore perfmon register, CPU software writes the ARI
request registers to specify
* whether the operation is a read or a write,
* which uncore perfmon register to access,
* the uncore perfmon unit, group, and counter number (if necessary),
* the data to write (if the operation is a write).
It then initiates an ARI request to run the uncore perfmon sequence in
the MCE and reads the resulting value of the uncore perfmon register
and any status information from the ARI response registers.
The NS world's MCE driver issues MCE_CMD_UNCORE_PERFMON_REQ command
for the EL3 layer to start the entire sequence. Once the request
completes, the NS world would receive the command status in the X0
register and the command data in the X1 register.
This patch implements the `get_target_pwr_state` handler for Tegra186
SoCs. The SoC port uses this handler to find out the cluster/system
state during CPU_SUSPEND, CPU_OFF and SYSTEM_SUSPEND calls.
The MCE firmware controls the power state of the CPU/CLuster/System,
so we query it to get the state and act accordingly.
Varun Wadekar [Fri, 24 Mar 2017 00:32:20 +0000 (17:32 -0700)]
Tegra186: mce: add the mce_update_cstate_info() helper function
This patch adds a helper function to the MCE driver to allow its
clients to issue UPDATE_CSTATE_INFO requests, without having to
setup the CPU context struct.
We introduced a struct to encapsulate the request parameters, that
clients can pass on to the MCE driver. The MCE driver gets the
parameters from the struct and programs the hardware accordingly.
Tegra186: reset CPU power state info while onlining
This patch resets the CPU power state info when we online any CPU. The
NS world software would re-init the CPU power state after the CPU gets
online anyways. This allows us to maintain proper CPU/cluster power
states in the MCE firmware at all times.
Soby Mathew [Mon, 13 Feb 2017 12:46:28 +0000 (12:46 +0000)]
Re-factor header files for easier PSCI library integration
This patch re-factors the following headers to make it easier to
integrate the PSCI library with an AArch32 Secure Payload :
* bl_common.h : The entry point information and the param
header data structures are factored out into separate
headers ep_info.h and param_headers.h
* psci.h : The PSCI library interfaces are factored out
into the new header psci_lib.h
* context_mgmt.h : The header file is modified to not include
arch.h when compiled for AArch32 mode.
No functional changes are introduced by this patch.
Summer Qin [Tue, 28 Feb 2017 16:46:17 +0000 (16:46 +0000)]
ARM platforms: Add support for MT bit in MPIDR
This patch modifies some of the functions in ARM platform layer to cater
for the case when multi-threading `MT` is set in MPIDR. A new build flag
`ARM_PLAT_MT` is added, and when enabled, the functions accessing MPIDR
now assume that the `MT` bit is set for the platform and access the bit
fields accordingly.
Also, a new API plat_arm_get_cpu_pe_count is added when `ARM_PLAT_MT` is
enabled, returning the PE count within the physical cpu corresponding to
`mpidr`.
This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.
Original change by Prashant Gaikwad <pgaikwad@nvidia.com>
Tegra186: enable support for simulation environment
The Tegra simulation environment has limited capabilities. This patch
checks the chip's major and minor versions to decide the features to
enable/disable - MCE firmware version checking is disabled and limited
Memory Controller settings are enabled
Varun Wadekar [Mon, 28 Mar 2016 23:00:02 +0000 (16:00 -0700)]
Tegra186: check MCE firmware version during boot
This patch checks that the system is running with the supported MCE
firmware during boot. In case the firmware version does not match the
interface header version, then the system halts.
Varun Wadekar [Mon, 28 Mar 2016 22:11:43 +0000 (15:11 -0700)]
Tegra186: fix programming sequence for SC7/SC8 entry
This patch fixes the programming sequence for 'System Suspend' and
'Quasi power down' state entry. The device needs to update the
required power state before querying the MCE firmware to see the
entry to that power state is allowed.
Varun Wadekar [Mon, 28 Mar 2016 22:05:03 +0000 (15:05 -0700)]
Tegra186: program default core wake mask during CPU_SUSPEND
This patch programs the default CPU wake mask during CPU_SUSPEND. This
reduces the CPU_SUSPEND latency as the system has to send one less SMC
before issuing the actual suspend request.
Original change by Krishna Sitaraman <ksitaraman@nvidia.com>
Varun Wadekar [Mon, 28 Mar 2016 20:44:35 +0000 (13:44 -0700)]
Tegra186: mce: enable LATIC for chip verification
This patch adds a new interface to allow for making an ARI call that
will enable LATIC for the chip verification software harness.
LATIC allows some MINI ISMs to be read in the CCPLEX. The ISMs are
used for various measurements relevant ot particular locations in
Silicon. They are small counters which can be polled to determine
how fast a particular location in the Silicon is.
Original change by Guy Sotomayor <gsotomayor@nvidia.com>
This patch adds support to save the BL31 state to the TZDRAM
before entering system suspend. The TZRAM loses state during
system suspend and so we need to copy the entire BL31 code to
TZDRAM before entering the state.
In order to restore the state on exiting system suspend, a new
CPU reset handler is implemented which gets copied to TZDRAM
during boot. TO keep things simple we use this same reset handler
for booting secondary CPUs too.
Varun Wadekar [Sat, 12 Mar 2016 01:18:51 +0000 (17:18 -0800)]
Tegra186: re-configure MSS' client settings
This patch reprograms MSS to make ROC deal with ordering of
MC traffic after boot and system suspend exit. This is needed
as device boots with MSS having all control but POR wants ROC
to deal with the ordering. Performance is expected to improve
with ROC but since no one has really tested the performance,
keep the option configurable for now by introducing a platform
level makefile variable.
Varun Wadekar [Thu, 3 Mar 2016 21:52:52 +0000 (13:52 -0800)]
Tegra186: implement support for System Suspend
This patch adds the chip level support for System Suspend entry
and exit. As part of the entry sequence we first query the MCE
firmware to check if it is safe to enter system suspend. Once
we get a green light, we save hardware block settings and enter
the power state. As expected, all the hardware settings are
restored once we exit the power state.
Varun Wadekar [Thu, 3 Mar 2016 21:09:08 +0000 (13:09 -0800)]
Tegra186: smmu: driver for the smmu hardware block
This patch adds a device driver for the SMMU hardware block on
Tegra186 SoCs. We use the generic ARM SMMU-500 IP block on
Tegra186. The driver only supports saving the SMMU settings
before entering system suspend. The MC driver and the NS world
clients take care of programming their own settings.
dp-arm [Tue, 7 Mar 2017 10:08:42 +0000 (10:08 +0000)]
mbedtls: Namespace TF specific macros
These macros are not part of mbed TLS so they should not be prefixed
with `MBEDTLS_` to avoid potential collision in the future. Use the
`TBBR_` suffix to highlight that they only used in TF.
`MBEDTLS_KEY_ALG` was not modified because that is documented and used
by platforms to select the key algorithm.
Douglas Raillard [Mon, 20 Mar 2017 10:38:29 +0000 (10:38 +0000)]
Tegra: replace ASM signed tests with unsigned
Replace the occurrences of signed condition codes where it was
unnecessary by an unsigned test as the unsigned tests allow the full
range of unsigned values to be used without inverting the result with
some large operands.
Varun Wadekar [Mon, 29 Feb 2016 18:24:30 +0000 (10:24 -0800)]
Tegra186: implement quasi power off (SC8) state
This patch adds support for the SC8 system power off state. This
state keeps the sensor subsystem powered ON while powering down
the remaining parts of the SoC. The CPUs and DRAM are powered down
as part of this state entry and perform a cold boot when exiting SC8.
Varun Wadekar [Wed, 17 Feb 2016 23:07:49 +0000 (15:07 -0800)]
Tegra: memctrl_v2: implement MC txn override WAR
This patch sets the Memory Controller's TXN_OVERRIDE registers
for most write clients to CGID_ADR. This ensures ordering is maintained.
In some cases WAW ordering problems could occur. There are different
settings for Tegra version A01 v A02.
Original changes by Alex Waterman <alexw@nvidia.com>
Varun Wadekar [Tue, 9 Feb 2016 22:55:44 +0000 (14:55 -0800)]
Tegra186: fix per-cpu wake times for CPU power states
This patch fixes the logic used to calculate the CPU index for
storing the per-cpu wake times. We use the MIDR register to
calculate the CPU index now. This allows us to store values for
Denver/A57 CPUs properly.
Varun Wadekar [Tue, 19 Jan 2016 03:03:19 +0000 (19:03 -0800)]
Tegra186: support for C6/C7 CPU_SUSPEND states
This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is
an idle state while C7 is a powerdown state.
The MCE block takes care of the entry/exit to/from these core power
states and hence we call the corresponding MCE handler to process
these requests. The NS driver passes the tentative time that the
core is expected to stay in this state as part of the power_state
parameter, which we store in a per-cpu array and pass it to the
MCE block.
Varun Wadekar [Wed, 30 Dec 2015 23:15:08 +0000 (15:15 -0800)]
Tegra: memctrl_v2: secure the on-chip TZSRAM memory
This patch programs the Memory controller's control registers
to disable non-secure accesses to the TZRAM. In case these
registers are already programmed by the BL2/BL30, then the
driver just bails out.
Varun Wadekar [Sat, 9 Jan 2016 01:38:51 +0000 (17:38 -0800)]
Tegra186: support for the latest platform port handlers
This patch adds support for the newer platform handler functions. Commit
I6db74b020b141048b6b8c03e1bef7ed8f72fd75b merges the upstream code which
has already moved all the upstream supported platforms over to these
handler functions.
Varun Wadekar [Mon, 30 Nov 2015 20:05:04 +0000 (12:05 -0800)]
Tegra186: relocate bl31.bin to the SYSRAM
Tegra186 has an on-die, 320KB, "System RAM" memory. Out of the total
size, 256KB are allocated for the CPU TrustZone binaries - EL3 monitor
and Trusted OS.
This patch changes the base address for bl31.bin to the SysRAM base
address. The carveout is too small for the Trusted OS, so we relocate
only the monitor binary.
This patch add code to power on/off the secondary CPUs on the Tegra186
chip. The MCE block is the actual hardware that takes care of the
power on/off sequence. We pass the constructed CPU #, depending on the
MIDR_IMPL field, to the MCE CPU handlers.
This patch also programs the reset vector addresses to allow the
CPUs to power on through the monitor and then jump to the linux
world.
Varun Wadekar [Tue, 14 Mar 2017 21:24:35 +0000 (14:24 -0700)]
Tegra186: mce: driver for the CPU complex power manager block
The CPU Complex (CCPLEX) Power Manager (Denver MCE, or DMCE) is an
offload engine for BPMP to do voltage related sequencing and for
hardware requests to be handled in a better latency than BPMP-firmware.
There are two interfaces to the MCEs - Abstract Request Interface (ARI)
and the traditional NVGINDEX/NVGDATA interface.
MCE supports various commands which can be used by CPUs - ARM as well
as Denver, for power management and reset functionality. Since the
linux kernel is the master for all these scenarios, each MCE command
can be issued by a corresponding SMC. These SMCs have been moved to
SiP SMC space as they are specific to the Tegra186 SoC.
Varun Wadekar [Tue, 25 Aug 2015 11:33:14 +0000 (17:03 +0530)]
Tegra186: platform support for Tegra "T186" SoC
Tegra186 is the newest SoC in the Tegra family which consists
of two CPU clusters - Denver and A57. The Denver cluster hosts
two next gen Denver15 CPUs while the A57 cluster hosts four ARM
Cortex-A57 CPUs. Unlike previous Tegra generations, all the six
cores on this SoC would be available to the system at the same
time and individual clusters can be powered down to conserve
power.
Change-Id: Id0c9919dbf5186d2938603e0b11e821b5892985e Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This patch adds driver for the Memory Controller (v2) in the newer
Tegra SoCs. The newer hardware uses ARM's SMMU hardware instead of
the proprietary block in the past.
dp-arm [Tue, 7 Mar 2017 11:02:47 +0000 (11:02 +0000)]
Move plat/common source file definitions to generic Makefiles
These source file definitions should be defined in generic
Makefiles so that all platforms can benefit. Ensure that the
symbols are properly marked as weak so they can be overridden
by platforms.
NOTE: This change is a potential compatibility break for
non-upstream platforms.
Andre Przywara [Thu, 6 Oct 2016 15:54:53 +0000 (16:54 +0100)]
Add workaround for ARM Cortex-A53 erratum 855873
ARM erratum 855873 applies to all Cortex-A53 CPUs.
The recommended workaround is to promote "data cache clean"
instructions to "data cache clean and invalidate" instructions.
For core revisions of r0p3 and later this can be done by setting a bit
in the CPUACTLR_EL1 register, so that hardware takes care of the promotion.
As CPUACTLR_EL1 is both IMPLEMENTATION DEFINED and can be trapped to EL3,
we set the bit in firmware.
Also we dump this register upon crashing to provide more debug
information.
Enable the workaround for the Juno boards.
Change-Id: I3840114291958a406574ab6c49b01a9d9847fec8 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
ge, lt, gt and le condition codes in assembly provide a signed test
whereas hs, lo, hi and ls provide the unsigned counterpart. Signed tests
should only be used when strictly necessary, as using them on logically
unsigned values can lead to inverting the test for high enough values.
All offsets, addresses and usually counters are actually unsigned
values, and should be tested as such.
Replace the occurrences of signed condition codes where it was
unnecessary by an unsigned test as the unsigned tests allow the full
range of unsigned values to be used without inverting the result with
some large operands.
Change-Id: I58b7e98d03e3a4476dfb45230311f296d224980a Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
Modify ARM common makefile to use version 2 of the translation tables
library and include the new header in C files.
Simplify header dependencies related to this library to simplify the
change.
The following table contains information about the size increase in
bytes for BL1 after applying this patch. The code has been compiled for
different configurations of FVP in AArch64 mode with compiler GCC 4.9.3 20150413. The sizes have been calculated with the output of `nm` by
adding the size of all regions and comparing the total size before and
after the change. They are sumarized in the table below:
text bss data total
Release +660 -20 +88 +728
Debug +740 -20 +242 +962
Debug (LOG_LEVEL=50) +1120 -20 +317 +1417
Change-Id: I539e307f158ab71e3a8b771640001fc1bf431b29 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
TLBI instructions for EL3 won't have the desired effect under specific
circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and
TLBI twice each time.
Even though this errata is only needed in r0p0, the current errata
framework is not prepared to apply run-time workarounds. The current one
is always applied if compiled in, regardless of the CPU or its revision.
This errata has been enabled for Juno.
The `DSB` instruction used when initializing the translation tables has
been changed to `DSB ISH` as an optimization and to be consistent with
the barriers used for the workaround.
Change-Id: Ifc1d70b79cb5e0d87e90d88d376a59385667d338 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Added APIs to add and remove regions to the translation tables
dynamically while the MMU is enabled. Only static regions are allowed
to overlap other static ones (for backwards compatibility).
A new private attribute (MT_DYNAMIC / MT_STATIC) has been added to
flag each region as such.
The dynamic mapping functionality can be enabled or disabled when
compiling by setting the build option PLAT_XLAT_TABLES_DYNAMIC to 1
or 0. This can be done per-image.
TLB maintenance code during dynamic table mapping and unmapping has
also been added.
Fixes ARM-software/tf-issues#310
Change-Id: I19e8992005c4292297a382824394490c5387aa3b Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
- Whenever multiple invalid descriptors are found, only the first one
is printed, and a line is added to inform about how many descriptors
have been omitted.
- At the beginning of each line there is an indication of the table
level the entry belongs to. Example of the new output:
`[LV3] VA:0x1000 PA:0x1000 size:0x1000 MEM-RO-S-EXEC`
Change-Id: Ib6f1cd8dbd449452f09258f4108241eb11f8d445 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
The files affected by this patch don't really depend on `xlat_tables.h`.
By changing the included file it becomes easier to switch between the
two versions of the translation tables library.
Change-Id: Idae9171c490e0865cb55883b19eaf942457c4ccc Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
The folder lib/xlat_tables_v2 has been created to store a new version
of the translation tables library for further modifications in patches
to follow. At the moment it only contains a basic implementation that
supports static regions.
This library allows different translation tables to be modified by
using different 'contexts'. For now, the implementation defaults to
the translation tables used by the current image, but it is possible
to modify other tables than the ones in use.
Added a new API to print debug information for the current state of
the translation tables, rather than printing the information while
the tables are being created. This allows subsequent debug printing
of the xlat tables after they have been changed, which will be useful
when dynamic regions are implemented in a patch to follow.
The common definitions stored in `xlat_tables.h` header have been moved
to a new file common to both versions, `xlat_tables_defs.h`.
All headers related to the translation tables library have been moved to
a the subfolder `xlat_tables`.
Change-Id: Ia55962c33e0b781831d43a548e505206dffc5ea9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Varun Wadekar [Fri, 17 Feb 2017 02:14:37 +0000 (18:14 -0800)]
spd: trusty: save context starting from the stack end
This patch uses the stack end to start saving the CPU context
during world switch. The previous logic, used the stack start
to save the context, thus overwriting the other members of the
context.
If Trusty is not running on the device, then Verified Boot is
not supported and the NS layer will fail gracefully later during
boot. This patch just returns success for the case when Trusty is
not running on the device and the bootloader issues SET_ROT_PARAMS
call during boot, so that we can at least boot non-Android images.
Varun Wadekar [Wed, 8 Jun 2016 04:21:59 +0000 (21:21 -0700)]
tlkd: execute standard SMC calls on the boot CPU
This patch checks if standard SMC calls, meant for TLK, are issued
only on the boot CPU. TLK is UP Trusted OS stack and so we need this
check to avoid the NS world calling into TLK from any other CPU.
The previous check tied TLK to CPU0, but the boot CPU can be other
than CPU0 in some scenarios.
Anthony Zhou [Wed, 20 Apr 2016 02:16:48 +0000 (10:16 +0800)]
spd: trusty: only process one function ID at a time
In multi-guest trusty environment, all guest's SMCs will be
forwarded to Trusty. This change only allows 1 guest's SMC
to be forwarded at a time and returns 'busy' status to all
other requests.
Change-Id: I2144467d11e3680e28ec816adeec2766bca114d4 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Anthony Zhou [Fri, 30 Oct 2015 22:03:41 +0000 (06:03 +0800)]
spd: trusty: pass VMID via X7
According to the ARM DEN0028A spec, hypervisor ID(VMID) should be stored
in x7 (or w7). This patch gets this value from the context and passes it
to Trusty. In order to do so, introduce new macros to pass five to eight
parameters to the Trusted OS.
Change-Id: I101cf45d0712e1e880466b2274f9a48af755c9fa Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
projects / arm-tf.git / log