Merge changes from topic "ls1046a" into integration
* changes:
docs(layerscape): add ls1046a soc and board support
feat(ls1046aqds): add board ls1046aqds support
feat(ls1046afrwy): add ls1046afrwy board support
feat(ls1046ardb): add ls1046ardb board support
feat(ls1046a): add new SoC platform ls1046a
fix(nxp-tools): fix tool location path for byte_swape
fix(nxp-qspi): fix include path for QSPI driver
build(changelog): add new scopes for NXP layerscape platforms
Merge changes from topic "st-format-signedness" into integration
* changes:
feat(stm32mp1): enable format-signedness warning
fix(stm32mp1): correct types in messages
fix(st-pmic): correct verbose message
fix(st-sdmmc2): correct cmd_idx type in messages
fix(st-fmc): fix type in message
fix(mtd): correct types in messages
fix(usb): correct type in message
fix(tzc400): correct message with filter
fix(psci): correct parent_node type in messages
fix(libc): correct some messages
fix(fconf): correct image_id type in messages
fix(bl2): correct messages with image_id
fix(fvp): extend memory map to include all DRAM memory regions
Currently only the lowest 2 DRAM region were configured in the
TrustZone Controller, but the platform supports 6 regions spanning the
whole address space.
Configuring all of them to allow tests to access memory also in those
higher memory regions.
FVP memory map:
https://developer.arm.com/documentation/100964/1116/Base-Platform/Base---memory/Base-Platform-memory-map
Note that last row is wrong, describing a non-existing 56bit address,
all region labels should be shifted upward.
Issue has been reported and next release will be correct.
Merge changes from topic "ea/corstone1000" into integration
* changes:
feat(corstone1000): identify bank to load fip
fix(corstone1000): change base address of FIP in the flash
feat(corstone1000): implement platform specific psci reset
feat(corstone1000): made changes to accommodate 3MB for optee
build(corstone1000): rename diphda to corstone1000
Satish Kumar [Wed, 27 Oct 2021 15:31:04 +0000 (16:31 +0100)]
feat(corstone1000): identify bank to load fip
Secure enclave decides the boot bank based on the firmware update
state of the system and updates the boot bank information at a given
location in the flash. In this commit, bl2 reads the given flash
location to indentify the bank from which it should load fip from.
fix(corstone1000): change base address of FIP in the flash
More space in the flash is reserved up front for metadata
parser and UEFI variables. That requires change in the flash
base address of where images are present.
Jiafei Pan [Thu, 20 Jan 2022 09:43:11 +0000 (17:43 +0800)]
feat(ls1046aqds): add board ls1046aqds support
ls1046aqds board is full function board to evaluate ls1046a platform.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Id1befe37a25f7c379e76791538348fd03bba78f7
Jiafei Pan [Thu, 20 Jan 2022 09:42:39 +0000 (17:42 +0800)]
feat(ls1046afrwy): add ls1046afrwy board support
The LS1046A Freeway board (FRWY) is a high-performance computing,
evaluation, and development platform that supports the LS1046A
architecture processor capable of support more than 32,000 CoreMark
performance. The FRWY-LS1046A board supports the LS1046A processor,
onboard DDR4 memory, multiple Gigabit Ethernet, USB3.0 and M2_Type_E
interfaces for Wi-Fi, FRWY-LS1046A-AC includes the Wi-Fi card.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I9a9680689e6f17bf4cc76fd5d1883eed6ace5149
Jiafei Pan [Thu, 20 Jan 2022 09:41:49 +0000 (17:41 +0800)]
feat(ls1046ardb): add ls1046ardb board support
The LS1046A reference design board (RDB) is a high-performance
computing, evaluation, and development platform that supports
the Layerscape LS1046A architecture processor.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: Ib7a01b309e0b0acc7f38e22b138e9e181dff244a
Jiafei Pan [Thu, 20 Jan 2022 09:40:16 +0000 (17:40 +0800)]
feat(ls1046a): add new SoC platform ls1046a
The LS1046A is a cost-effective, power-efficient, and highly
integrated system-on-chip (SoC) design that extends the reach
of the NXP value-performance line of QorIQ communications
processors. Featuring power-efficient 64-bit Arm Cortex A72
cores with ECC-protected L1 and L2 cache memories for high
reliability, running up to 1.8 GHz.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Signed-off-by: rocket <rod.dorris@nxp.com> Signed-off-by: Biwen Li <biwen.li@nxp.com>
Change-Id: I208d9bf1702410463c2b2630d31d0cd4eb7e8837
Jiafei Pan [Thu, 10 Feb 2022 02:39:56 +0000 (10:39 +0800)]
build(changelog): add new scopes for NXP layerscape platforms
1. Add scopes for ls1046a and related boards: ls1046ardb,
ls1046aqds, ls1046afwry.
2. Add new scope for NXP QSPI driver.
3. Add new scope for NXP tools.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I68ef7dd25628b393dbfbb8dbf59d5185945ea61c
Arpita S.K [Wed, 13 Oct 2021 09:19:26 +0000 (14:49 +0530)]
feat(corstone1000): made changes to accommodate 3MB for optee
These changes are required to accommodate 3MB for OP-TEE and this
is required for SP's part of optee
Added size macro's for better readability of the code
Moved uboot execution memory from CVM to DDR
Yann Gautier [Wed, 9 Feb 2022 13:03:35 +0000 (14:03 +0100)]
refactor(stm32mp1): move PIE flag to SP_min
The PIE compilation is used only for BL32, move the ENABLE_PIE to
sp_min-stm32mp1.mk file. Override PIE flags, as sp_min.mk file is
included after the flags are set in Makefile.
The BL2_IN_XIP_MEM was added for a feature not yet upstreamed.
It is then removed from platform.mk file.
Change-Id: If055e51e0f160f99cd4e4cf68ca718d4d693119c Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Toromanoff <nicolas.toromanoff@foss.st.com>
docs(contribution-guidelines): updated the build configuration section
Added a couple of sub-sections (Coverity Scan and Test Configuration)
under "Add build configuration" to update the patch owners on the
sections they need to be aware of while introducing new source files.
Andre Przywara [Thu, 27 Jan 2022 17:47:55 +0000 (17:47 +0000)]
fix(libc): snprintf: include stdint.h
The snprintf code uses the uintptr_t type, which is defined in stdint.h.
We do not include this header explicitly, but get the definition
indirectly through some other header doing so.
However this breaks when snprintf is compiled in isolation (for instance
for unit-testing), so let's add this #include to make things right.
Change-Id: I1299767ee482f5cf1af30c4df2e8f7e596969b41 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara [Mon, 24 Jan 2022 18:16:10 +0000 (18:16 +0000)]
fix(libc): limit snprintf radix value
In our unsigned_num_print() function we first print the integer into a
local buffer, then put this through alignment and padding and output the
result. For this we use a local buffer, sized by the maximum possible
length of the largest possible number.
However this assumes that the radix is not smaller than 10, which is
indeed the smallest value we pass into this static function at the
moment. To prevent accidents in the future, should we add support for
other radices, add an assert to enforce our assumption.
Unfortunately this cannot be a static assert (CASSERT), since the
compiler is not smart enough to see that the argument is always coming
from a literal.
Change-Id: Ic204462600d9f4c281d899cf9f2c698a0a33a874 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Manish Pandey [Wed, 9 Feb 2022 14:05:47 +0000 (15:05 +0100)]
Merge changes from topic "db/exception_pstate" into integration
* changes:
test(el3-runtime): dit is retained on world switch
fix(el3-runtime): set unset pstate bits to default
refactor(el3-runtime): add prepare_el3_entry func
Andre Przywara [Tue, 21 Dec 2021 12:35:54 +0000 (12:35 +0000)]
fix(libc): fix snprintf corner cases
The number formatting routine in snprintf was trying to be clever with
the buffer handling, but tripped over its own feet: snprintf() users
expect output to be emitted, even if not everything fits into the
buffer. The current code gives up completely when the buffer is too
small.
Fix those issues and simplify the code on the way, by consequently using
the CHECK_AND_PUT_CHAR() macro, which both checks for the buffer size
correctly, but also keeps track of the number of should-be-printed
characters for the return value.
Change-Id: Ifd2b03b9a73f9279abed53081a2d88720ecbdbc1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Aditya Angadi [Mon, 9 Aug 2021 04:08:58 +0000 (09:38 +0530)]
feat(rdn2): add board support for rdn2cfg2 variant
Add board support for variant 2 of RD-N2 platform which is a four chip
variant with 4 cores on each chip. The "CSS_SGI_PLATFORM_VARIANT" value
is 2 for multi-chip variant. The "CSS_SGI_CHIP_COUNT_MACRO" can be in
the range [1, 4] for multi-chip variant.
Jorge Troncoso [Thu, 3 Feb 2022 23:52:59 +0000 (15:52 -0800)]
fix(ufs): don't zero out the write buffer
Previously ufs_write_blocks was memsetting the write buffer before
calling ufs_prepare_cmd, causing zeros to be written to UFS. This change
deletes the memset call so the original buffer contents get written to
UFS.
Manish Pandey [Thu, 3 Feb 2022 21:59:34 +0000 (22:59 +0100)]
Merge changes from topic "msm8916" into integration
* changes:
feat(msm8916): allow booting secondary CPU cores
feat(msm8916): setup hardware for non-secure world
feat(gic): allow overriding GICD_PIDR2_GICV2 address
feat(msm8916): initial platform port
docs(msm8916): new port for Qualcomm Snapdragon 410
Stephan Gerhold [Wed, 1 Dec 2021 19:04:44 +0000 (20:04 +0100)]
feat(msm8916): allow booting secondary CPU cores
Add support for the PSCI CPU_ON call to allow booting secondary CPU
cores. On cold boot they need to be booted with a special register
sequence. Also, the "boot remapper" needs to be configured to point to
the BL31_BASE, so the CPUs actually start executing BL31 after reset.
Change-Id: I406c508070ccb046bfdefd51554f12e1db671fd4 Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Stephan Gerhold [Wed, 1 Dec 2021 19:03:33 +0000 (20:03 +0100)]
feat(msm8916): setup hardware for non-secure world
Booting e.g. Linux in the non-secure world does not work with the
msm8916 port yet because essential hardware is not made available to
the non-secure world. Add more platform initialization to:
- Initialize the GICv2 and mark secure interrupts.
Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2
register address in platform_def.h to avoid a failing assert()
because of a (hardware) mistake in Qualcomm's GICv2 implementation.
- Make a timer frame available to the non-secure world.
The "Qualcomm Timer" (QTMR) implements the ARM generic timer
specification, so the standard defines (CNTACR_BASE etc)
can be used.
- Make parts of the "APCS" register region available to the
non-secure world, e.g. for CPU frequency control implemented
in Linux.
- Initialize a platform-specific register to route all SMMU context
bank interrupts to the non-secure interrupt pin, since all control
of the SMMUs is left up to the non-secure world for now.
Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Older Qualcomm SoCs seem to have a custom Qualcomm implementation of
the GICv2 specification. It's mostly compliant but unfortunately it
looks like a mistake was made with the GICD_PIDR registers. PIDR2 is
defined to be at offset 0xFE8, but the Qualcomm implementation has it
at 0xFD8.
It looks like the entire PIDR0-3/4-7 block is swapped compared to the
ARM implementation: PIDR0 starts at 0xFD0 (instead of 0xFE0)
and PIDR4 starts at 0xFE0 (instead of 0xFD0).
Actually this only breaks a single assert in gicv2_main.c that checks
the GIC version: assert((gic_version == ARCH_REV_GICV2) ...
In release mode everything seems to work correctly.
To keep the code generic, allow affected platforms to override the
GICD_PIDR2_GICV2 register address in platform_def.h. Since this header
is typically included very early (e.g. from assert.h), add an #ifndef
so the definitions from platform_def.h takes priority.
Change-Id: I2929a8c1726f8d751bc28796567eb30b81eca2fe Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Daniel Boulby [Fri, 22 Oct 2021 10:37:34 +0000 (11:37 +0100)]
test(el3-runtime): dit is retained on world switch
Add tsp service to check the value of the PSTATE DIT bit is as
expected and toggle it's value. This is used to ensure that
the DIT bit is maintained during a switch from the Normal to
Secure worlds and back.
Change-Id: I4e8bdfa6530e5e75925c0079d4fa2795133c5105 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Daniel Boulby [Tue, 25 May 2021 17:09:34 +0000 (18:09 +0100)]
fix(el3-runtime): set unset pstate bits to default
During a transition to a higher EL some of the PSTATE bits are not set
by hardware, this means that their state may be leaked from lower ELs.
This patch sets those bits to a default value upon entry to EL3.
This patch was tested using a debugger to check the PSTATE values
are correctly set. As well as adding a test in the next patch to
ensure the PSTATE in lower ELs is still maintained after this change.
Change-Id: Ie546acbca7b9aa3c86bd68185edded91b2a64ae5 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Stephan Gerhold [Wed, 1 Dec 2021 19:01:11 +0000 (20:01 +0100)]
feat(msm8916): initial platform port
Introduce the bare mimimum base of the msm8916 BL31 port. This is
pretty much just a standard platform "skeleton" with CPU/memory
initialization and an UART driver. This allows booting into
e.g. U-Boot with working UART output.
Note that the plat/qti/msm8916 port is completely separate and does not
make use of anything in plat/qti/common at the moment. The main reason
for that is that plat/qti/common is heavily focused around having a
binary "qtiseclib" component, while the MSM8916 port is fully
open-source (and therefore somewhat limited to publicly documented
functionality).
In the future it might be possible to re-use some of the open-source
parts in plat/qti/common (e.g. spmi_arb.c or pm_ps_hold.c) but it's
not strictly required for the basic functionality supported so far.
Change-Id: I7b4375df0f947b3bd1e55b0b52b21edb6e6d175b Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Stephan Gerhold [Wed, 1 Dec 2021 19:00:00 +0000 (20:00 +0100)]
docs(msm8916): new port for Qualcomm Snapdragon 410
The Qualcomm Snapdragon 410 is Qualcomm's first 64-bit SoC, released
in 2014 with four ARM Cortex-A53 cores. There are differents variants
(MSM8916, APQ8016(E), ...) that are all very similar. A popular device
based on APQ8016E is the DragonBoard 410c single-board computer,
but the SoC is also used in various mid-range smartphones/tablets.
This commit adds documentation for a minimal, community-maintained port
of TF-A/BL31 for MSM8916. The actual platform port is added in the
following four separate small commits to simplify the review process.
The code is primarily based on the information from the public
Snapdragon 410E Technical Reference Manual [1], combined with a lot of
trial and error to actually make it work.
Note that this port is a pure community effort without any
commercial interests and is not related to Qualcomm in any way.
The main motivation for this port is to have a minimal, updatable
firmware since this old chip does not receive many updates anymore from
Qualcomm. It works quite well for many use cases so I am willing to
maintain it as a "code owner". I have also added Nikita Travkin as
second code owner to help with reviews.
The main limitation so far is the lack of memory protection for TF-A.
This is similar to the ports for the Raspberry Pi but in this case not
a lack of hardware support but rather a lack of documentation. However,
this does not limit the usefulness of the port when used as a minimal
PSCI implementation.
Yann Gautier [Mon, 18 Oct 2021 08:55:23 +0000 (10:55 +0200)]
feat(st): add early console in BL2
Add an early UART console to ease debug before UART is fully configured.
This is done under flag STM32MP_EARLY_CONSOLE in the first STM32MP1
platform function called (bl2_el3_early_platform_setup()). It uses the
parameters defined for crash console: STM32MP_DEBUG_USART* macros.
Manish Pandey [Wed, 2 Feb 2022 21:17:12 +0000 (22:17 +0100)]
Merge changes from topic "st-security-update" into integration
* changes:
feat(stm32mp1): warn when debug enabled on secure chip
fix(stm32mp1): rework switch/case for MISRA
feat(st): disable authentication based on part_number
Manish Pandey [Wed, 2 Feb 2022 17:41:08 +0000 (18:41 +0100)]
Merge changes I5d7e3cf3,Ie81f2fc5,If869ac93,I2cf2badf,Ic291eb13 into integration
* changes:
fix(sptool): add leading zeroes in UUID conversion
feat(tc): enable SMMU for DPU
feat(tc): add reserved memory region for Gralloc
feat(tc): enable GPU
fix(tc): remove the bootargs node
Merge changes from topic "st-gpio-update" into integration
* changes:
feat(st-gpio): do not apply secure config in BL2
feat(st): get pin_count from the gpio-ranges property
feat(st-gpio): allow to set a gpio in output mode
refactor(st-gpio): code improvements
The Event Log sources are added to the source-list of BL1 and BL2
images in the Event Log Makefile. It doesn't seem correct since
some platforms only compile Event Log sources for BL2.
Hence, moved compilation decision of Event Log sources to the
platform makefile.
Change-Id: I1cb96e24d6bea5e091d08167f3d1470d22b461cc Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Yann Gautier [Tue, 11 Aug 2020 12:21:41 +0000 (14:21 +0200)]
feat(st-gpio): do not apply secure config in BL2
At boot, the devices under ETZPC control are secured, so should be
their GPIOs. As securable GPIOs are secured by default, keep the reset
values in BL2.
feat(st): get pin_count from the gpio-ranges property
The "ngpios" property is deprecated and may be removed.
Use the "gpio-ranges" property where the last parameter of that
property is the number of available pins within that range.
No functional, change, but some improvements:
- Declare set_gpio() as static (only called locally)
- Handle the type ('open-drain') property independently from the
mode one.
- Replace mmio_clrbits_32() + mmio_setbits_32() with
mmio_clrsetbits_32().
- Add a missing log
- Add missing U() in macro definitions
Yann Gautier [Tue, 19 Oct 2021 11:31:06 +0000 (13:31 +0200)]
fix(stm32mp1): rework switch/case for MISRA
Avoid the use of return inside switch/case in stm32mp_is_single_core().
Although this MISRA rulre might not be enforced, we align on what is done
for stm32mp_is_auth_supported().
Lionel Debieve [Fri, 6 Dec 2019 11:42:20 +0000 (12:42 +0100)]
feat(st): disable authentication based on part_number
STM32MP15xA and STM32MP15xD chip part numbers don't
support the secure boot.
All functions linked to secure boot must not be used
and signed binaries are not allowed on such chip.
Daniel Boulby [Wed, 19 Jan 2022 11:20:05 +0000 (11:20 +0000)]
refactor(el3-runtime): add prepare_el3_entry func
In the next patch we add an extra step of setting the PSTATE
registers to a known state on el3 entry. In this patch we create
the function prepare_el3_entry to wrap the steps needed for before
el3 entry. For now this is only save_gp_pmcr_pauth_regs.
Change-Id: Ie26dc8d89bfaec308769165d2649e84d41be196c Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
The monotonic counter is stored in an OTP fuse.
A check is done in TF-A.
If the TF-A version is incremented, then the counter will be updated
in the corresponding OTP.
Lionel Debieve [Mon, 4 Nov 2019 13:31:38 +0000 (14:31 +0100)]
feat(stm32mp1): new way to access platform OTP
Use dt_find_otp_name() to retrieve platform OTP information
from device tree, directly or through stm32_get_otp_index() and
stm32_get_otp_value() platform services.
String definitions replace hard-coded values, they are used to call
this new function.
Change-Id: I81213e4a9ad08fddadc2c97b064ae057a4c79561 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
Nicolas Le Bayon [Tue, 10 Sep 2019 12:18:27 +0000 (14:18 +0200)]
feat(stm32mp1-fdts): update NVMEM nodes
Set non-secure property on platform secure OTP nodes that non-secure
world is allowed to access through secure world services.
These are the SoC MAC address and the ST boards board_id OTPs.
Most of these were already done but it was missing for ED1 board.
Change-Id: Idfa6322d9d5c35285706d0b2d32ae09af38684a7 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Nicolas Le Bayon [Mon, 20 May 2019 16:35:02 +0000 (18:35 +0200)]
refactor(st-drivers): improve BSEC driver
Rename driver file to BSEC2.
Split header file in IP and feature parts.
Add functions to access BSEC scratch register.
Several corrections and improvements.
Probe the driver earlier, especially to check debug features.
Change-Id: I1981536398d598d67a19d2d7766dacc18de72ec1 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
Nicolas Le Bayon [Fri, 25 Sep 2020 15:25:09 +0000 (17:25 +0200)]
feat(stm32mp1-fdts): add nvmem_layout node and OTP definitions
A new nvmem_layout node includes nvmem platform-dependent layout
information, such as OTP NVMEM cell lists (phandle, name).
This list allows easy access to OTP offsets defined in BSEC node,
where more OTP definitions with offsets in bytes and length have
been added (replace hard-coded values).
Each board may redefine this list, especially for board_id info.
Change-Id: I910ae671b3bf3320ee6500fecc9ec335ae67bbda Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
This patch adds the basic CPU library code to support the Poseidon CPU
in TF-A. Poseidon is derived from HunterELP core, an implementation of
v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP,
is supported in TF-A. Accordingly the Hunter CPU library code has been
as the base and adapted here.
projects / arm-tf.git / log