Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
fix(intel): extending to support large file size for AES encryption and decryption
feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
fix(intel): update certificate mask for FPGA Attestation
feat(intel): update to support maximum response data size
feat(intel): support ECDSA HASH Verification
feat(intel): support ECDSA HASH Signing
feat(intel): support ECDH request
feat(intel): support ECDSA SHA-2 Data Signature Verification
feat(intel): support ECDSA SHA-2 Data Signing
feat(intel): support ECDSA Get Public Key
feat(intel): support session based SDOS encrypt and decrypt
feat(intel): support AES Crypt Service
feat(intel): support HMAC SHA-2 MAC verify request
feat(intel): support SHA-2 hash digest generation on a blob
feat(intel): support extended random number generation
feat(intel): support crypto service key operation
feat(intel): support crypto service session
feat(intel): extend attestation service to Agilex family
fix(intel): flush dcache before sending certificate to mailbox
fix(intel): introduce a generic response error code
fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
feat(intel): single certificate feature enablement
feat(intel): initial commit for attestation service
fix(intel): update encryption and decryption command logic
Bipin Ravi [Wed, 22 Dec 2021 20:35:21 +0000 (14:35 -0600)]
fix(errata): workaround for DSU-110 erratum 2313941
DSU-110 erratum 2313941 is a Cat B erratum and applies to revisions
r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open.
The workaround sets IMP_CLUSTERACTLR_EL1[16:15] bits to 0b11 to disable
clock gating of the SCLK domain. This will increase the idle power
consumption.
This patch applies the fix for Cortex-X2/A510/A710 and Neoverse N2.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1781796/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I54d948b23e8e01aaf1898ed9fe4e2255dd209318 Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Sieu Mun Tang [Thu, 28 Apr 2022 08:28:48 +0000 (16:28 +0800)]
fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
This patch is to extend to support large file size
for SHA2/HMAC get digest and verifying. The large
file will be split into smaller chunk and send using
initialize, update and finalize staging method.
Signed-off-by: Yuslaimi, Alif Zakuan <alif.zakuan.yuslaimi@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I1815deeb61287b32c3e77c5ac1b547b79ef12674
Sieu Mun Tang [Thu, 28 Apr 2022 08:23:20 +0000 (16:23 +0800)]
fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
This patch is to extend to support large file size
for SHA-2 ECDSA data signing and signature verifying.
The large file will be split into smaller chunk and
send using initialize, update and finalize staging method.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: If277b2b375a404fe44b0858006c8ba6316a5ce23
Sieu Mun Tang [Thu, 28 Apr 2022 08:15:54 +0000 (16:15 +0800)]
fix(intel): extending to support large file size for AES encryption and decryption
This patch is to extend to support large file size
for AES encryption and decryption. The large file
will be split into smaller chunk and send using
initialize, update and finalize staging method.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ie2ceaf247e0d7082aad84faf399fbd18d129c36a
Boon Khai Ng [Mon, 30 Aug 2021 07:05:49 +0000 (15:05 +0800)]
fix(intel): update certificate mask for FPGA Attestation
Update the certificate mask to 0xff to cover all certificate
in Agilex family.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Id40bc3aa4b3e4f7568a58581bbb03a75b0f20a0b
Sieu Mun Tang [Wed, 11 May 2022 02:23:13 +0000 (10:23 +0800)]
feat(intel): update to support maximum response data size
Update to support maximum (4092 bytes) response data size.
And, clean up the intel_smc_service_completed function to
directly write the response data to addr to avoid additional
copy.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I0a230e73c563d22e6999ad3473587b07382dacfe
Sieu Mun Tang [Tue, 10 May 2022 09:53:32 +0000 (17:53 +0800)]
feat(intel): support ECDSA HASH Verification
Supporting the command to send digital signature verification
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ic86f531bfe7cc7606699f2b064ac677aaf806a76
Sieu Mun Tang [Tue, 10 May 2022 09:50:30 +0000 (17:50 +0800)]
feat(intel): support ECDSA HASH Signing
Supporting the command to send digital signature signing
request on a data blob. This include ECC algorithm such as
NISP P-256, NISP P-384, Brainpool 256 and, Branpool 384
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I12cf0f1ceaf07c33a110eae398d3ad82a9b13d38
Sieu Mun Tang [Tue, 10 May 2022 09:36:32 +0000 (17:36 +0800)]
feat(intel): support ECDSA Get Public Key
To support the ECDSA feature and send the command
as a request to get the public key
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9d7bb5b6ab8ef7d4f3ceb21ff0068baf3175a1ac
Sieu Mun Tang [Mon, 9 May 2022 08:05:58 +0000 (16:05 +0800)]
feat(intel): support session based SDOS encrypt and decrypt
Extends existing Secure Data Object Service (SDOS) encryption and
decryption mailbox command to include session id and context id. The
new format requires an opened crypto service session.
A separated SMC function ID is introduced for the new format and it is
only supported by Agilex.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I2627750e8337c1af66217e9cb45981a9e06e7d19
Sieu Mun Tang [Tue, 10 May 2022 09:30:00 +0000 (17:30 +0800)]
feat(intel): support AES Crypt Service
Enable Support for AES Crypt Service to send request
to encrypt or decrypt a blob. Command will send a memory
location that SDM will read and also memory location that
SDM will write back after encryption or decryption operation.
Response will be sent back after the crypto operation is done,
and data is written back to the destination
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86ea4ff64dda2fbb1000591e30fa8cb2640ce954
Sieu Mun Tang [Tue, 10 May 2022 09:27:12 +0000 (17:27 +0800)]
feat(intel): support HMAC SHA-2 MAC verify request
This command sends request on checking the integrity and authenticity
of a blob by comparing the calculated MAC with tagged MAC. The
comparison result will be returned in response.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ifefdf67f088d7612d2ec2459d71faf2ec8181222
Sieu Mun Tang [Tue, 10 May 2022 09:18:19 +0000 (17:18 +0800)]
feat(intel): support extended random number generation
The random number generation (RNG) mailbox command format
is updated to extends the support to upto 4080 bytes random
number generation. The new RNG format requires an opened
crypto service session.
A separated SMC function ID is introduced for the new RNG
format and it is only supported by Agilex.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3f044a3c01ff7cb50be4705e2c1f982bf6f61432
fix(st-spi): always check SR_TCF flags in stm32_qspi_wait_cmd()
Currently, SR_TCF flag is checked in case there is data, this criteria
is not correct.
SR_TCF flags is set when programmed number of bytes have been
transferred to the memory device ("bytes" comprised command and data
send to the SPI device).
So even if there is no data, we must check SR_TCF flag.
Sieu Mun Tang [Mon, 9 May 2022 06:16:14 +0000 (14:16 +0800)]
feat(intel): support crypto service key operation
Support crypto service key operation mailbox commands through SMC.
Crypto service key operation begin by sending an open crypto service
session request to SDM firmware. Once successfully open the session,
send crypto service key management commands (import, export, remove
and get key info) with the associated session id to SDM firmware.
The crypto service key is required before perform any crypto service
(encryption, signing, etc). Last, close the session after finishes
crypto service. All crypto service keys associated with this session
will be erased by SDM firmware.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I02406533f38b9607eb1ec7e1395b9dc2d084a9e3
Sieu Mun Tang [Mon, 9 May 2022 04:08:42 +0000 (12:08 +0800)]
feat(intel): support crypto service session
Support crypto service open and close session mailbox commands through
SMC.
Crypto service support begin by sending an open crypto service session
request to SDM firmware. Last, close the session after finishes crypto
service. All crypto service parameters with this session will be erased
by SDM firmware.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I48968498bbd6f2e71791f4ed38dd5f369e171082
Sieu Mun Tang [Mon, 9 May 2022 02:48:53 +0000 (10:48 +0800)]
feat(intel): extend attestation service to Agilex family
This patch extends the functionality of FPGA Crypto Services (FCS) to
support FPGA Attestation feature in Agilex device.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I3c2e29d2fa04d394e9f65d8143d7f4e57389cd02
Boon Khai Ng [Tue, 25 May 2021 17:50:34 +0000 (01:50 +0800)]
fix(intel): flush dcache before sending certificate to mailbox
Due to the cache coherency issue the dcache need to flush
before sending the certificate to the mailbox
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I39d5144519d9c7308597698b4cbea1b8aba0a849
Sieu Mun Tang [Tue, 12 Apr 2022 07:00:13 +0000 (15:00 +0800)]
fix(intel): introduce a generic response error code
This patch will introduce a generic error code (0x3ff)
to be used in case where Secure Device Manager (SDM)
mailbox request is not failing (returns OK with no error
code) but BL31 instead wants to return error/reject
to the calling software. This value aligns with generic
error code implemented in SDM for consistency.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I9894c7df8897fff9aa80970940a6f3f6bfa30bb7
Sieu Mun Tang [Fri, 6 May 2022 16:50:37 +0000 (00:50 +0800)]
fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
Allows non-secure software to access FPGA Crypto Services (FCS)
through secure monitor calls (SMC).
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I805b3f650abf5e118e2c55e469866d5d0ca68048
Sieu Mun Tang [Wed, 11 May 2022 02:01:54 +0000 (10:01 +0800)]
feat(intel): single certificate feature enablement
Extend the functionality of FPGA Crypto Service
(FCS) to support FPGA single certificate feature
so that the counter value can be updated with
only one preauthorized certificate
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibde87e4ee46367cf7f27f7bb0172838ab8766340
Sieu Mun Tang [Wed, 11 May 2022 01:59:55 +0000 (09:59 +0800)]
feat(intel): initial commit for attestation service
This is to extend the functionality of FPGA Crypto Service (FCS)
to support FPGA Attestation feature in Stratix 10 device.
Signed-off-by: Boon Khai Ng <boon.khai.ng@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ib15783383dc9a06a2f0dc6dc1786f44b89f32cb1
Sieu Mun Tang [Wed, 11 May 2022 01:49:25 +0000 (09:49 +0800)]
fix(intel): update encryption and decryption command logic
This change is to re-align HPS cryption logic with
underlying Secure Device Manager's (SDM) mailbox API.
Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I8fc90982d3cddceaf401c1a112ff8e20861bf4c5
Olivier Deprez [Tue, 10 May 2022 13:18:36 +0000 (15:18 +0200)]
Merge changes from topic "ffa_el3_spmc" into integration
* changes:
feat(spmc): add helper to obtain a partitions FF-A version
feat(spmd): enable SPMD to forward FFA_VERSION to EL3 SPMC
feat(spmc): enable handling FFA_VERSION ABI
feat(spmc): add helper function to obtain endpoint mailbox
feat(spmc): add helper function to obtain hyp structure
feat(spmc): enable parsing of messaging methods from manifest
Marc Bonnici [Thu, 9 Dec 2021 11:32:30 +0000 (11:32 +0000)]
feat(spmc): add helper to obtain a partitions FF-A version
Add a helper function to obtain the FF-A version of a calling
partition. This is used to ensure that the SPMC maintains
backwards compatibility if the partition implements a lower
minor version for the same major version than the SPMC.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I5b364a1e510a999bb0c4cacae28f23f8a42a1e3e
Marc Bonnici [Wed, 8 Dec 2021 14:27:40 +0000 (14:27 +0000)]
feat(spmd): enable SPMD to forward FFA_VERSION to EL3 SPMC
In order to allow the EL3 SPMC to know the FF-A version of the
entity running in the normal world, allow the SPMD to
forward the call rather than replying on its behalf.
This solution works as the EL3 can ERET directly back to
the calling partition however this is not an option
when the SPMC resides in a lower exception level. A new
approach will be required to support such scenario.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ic2d6e49c06340167eadefe893c6e1e20b67ab498
Marc Bonnici [Wed, 8 Dec 2021 14:24:03 +0000 (14:24 +0000)]
feat(spmc): enable handling FFA_VERSION ABI
Report the SPMC version to the caller, currently v1.1 and
also store the requested version to allow the SPMC to
use the corresponding FF-A version in future ABI calls.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I79aafd1e6694cbd4b231bbd0cac5834a71063d79
Marc Bonnici [Wed, 24 Nov 2021 10:33:48 +0000 (10:33 +0000)]
feat(spmc): add helper function to obtain endpoint mailbox
Add a helper function to obtain the relevant mailbox buffers
depending on which entity was last run. This will be used in
subsequent functionality to populate requested information in
the callers RX buffer.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I85959ced4d1454be05a7b3fb6853ed3ab7f0cf3e
Marc Bonnici [Wed, 24 Nov 2021 10:32:16 +0000 (10:32 +0000)]
feat(spmc): add helper function to obtain hyp structure
We assume that the first descriptor in the normal world
endpoints is reserved for the hypervisor and add a helper
function to enable retrieving this directly.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I67c3589994eb820ef420db6ab7e8bd0825d64455
Marc Bonnici [Thu, 9 Dec 2021 18:34:02 +0000 (18:34 +0000)]
feat(spmc): enable parsing of messaging methods from manifest
Ensure that the `messaging-methods` entry is populated in
an SP's manifest. Currently only direct messaging is supported
so alert if this does not match the manifest entry.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I67f1fad71a3507627993a004e0f8579388faf178
kadabi [Mon, 28 Feb 2022 22:21:09 +0000 (14:21 -0800)]
feat(snprintf): add support for length specifiers
Add long, long long and size_t length specifiers to
snprintf similar to vprintf. This will help capturing
all the UART logs into a logbuffer and makes snprintf
functionally equivalent to vprintf.
John Powell [Tue, 3 May 2022 20:52:11 +0000 (15:52 -0500)]
fix(errata): workaround for Cortex-A78 erratum 2395406
Cortex-A78 erratum 2395406 is a cat B erratum that applies to revisions
r0p0 - r1p2 and is still open. The workaround is to set bit[40] of
CPUACTLR2 which will disable folding of demand requests into older
prefetches with L2 miss requests outstanding.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: If06f988f05f925c2a4bed3e6a9414b6acdfec894
johpow01 [Wed, 9 Mar 2022 22:23:04 +0000 (16:23 -0600)]
fix(errata): workaround for Cortex-A710 erratum 2008768
Cortex-A710 erratum 2008768 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to clear
the ED bit in each ERXCTLR_EL1 register before setting the PWRDN bit in
CPUPWRCTLR_EL1.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ib2171c06da762dd4155b02c03d86766f1616381d
John Powell [Tue, 3 May 2022 20:22:57 +0000 (15:22 -0500)]
fix(errata): workaround for Cortex-A78 erratum 2376745
Cortex-A78 erratum 2376745 is a cat B erratum that applies to revisions
r0p0 - r1p2 and is still open. The workaround is to set bit[0] of
CPUACTLR2 which will force PLDW/PFRM ST to behave like PLD/PRFM LD and
not cause invalidation to other PE caches.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I6f1a3a7d613c5ed182a7028f912e0f6ae3aa7f98
Olivier Deprez [Mon, 9 May 2022 15:34:02 +0000 (17:34 +0200)]
fix(cm): add barrier before el3 ns exit
In cm_prepare_el3_exit_ns, SCR_EL3.NS bit change (to non-secure) is not
committed before the EL2 restoration sequence happens.
At ICC_SRE_EL2 write in cm_el2_sysregs_context_restore, NS is still 0
from CPU perspective (with EEL2=0) which is an invalid condition and
triggers a fault. By adding ISB, SCR_EL3 gets synced with NS=1/EEL2=0
before ICC_SRE_EL2 write.
Manish Pandey [Mon, 9 May 2022 09:30:50 +0000 (11:30 +0200)]
Merge changes Idfd268cd,I362445b9,Ibea052d3,I28cb8f74,I501ae76a, ... into integration
* changes:
feat(imx8mp): enable BL32 fdt overlay support on imx8mp
feat(imx8mq): enable optee fdt overlay support
feat(imx8mn): enable optee fdt overlay support
feat(imx8mm): enable optee fdt overlay support
feat(imx8mp): add trusty for imx8mp
feat(imx8mq): enable trusty for imx8mq
feat(imx8mn): enable Trusty OS for imx8mn
feat(imx8mm): enable Trusty OS on imx8mm
feat(imx8/imx8m): switch to xlat_tables_v2
feat(imx8m): enable the coram_s tz by default on imx8mn/mp
feat(imx8m): enable the csu init on imx8m
feat(imx8m): add a simple csu driver for imx8m family
refactor(imx8m): replace magic number with enum type
feat(imx8m): add imx csu/rdc enum type defines for imx8m
fix(imx8m): check the validation of domain id
feat(imx8m): enable conditional build for SDEI
Jacky Bai [Tue, 7 Jan 2020 06:53:54 +0000 (14:53 +0800)]
feat(imx8m): enable the csu init on imx8m
Enable the CSU init on i.MX8M SoC family. The 'csu_cfg' array
is just a placeholder for now as example with limited config listed.
In real use case,user can add the CSU config as needed based on system design.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I1f7999efa346f18f6625ed8c478d088ed75f7833
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10
Yann Gautier [Fri, 6 May 2022 13:27:32 +0000 (15:27 +0200)]
fix(st): add missing header include
This issue is triggered when enabling -Wmissing-prototypes:
plat/st/common/bl2_io_storage.c:114:5: warning: no previous prototype
for 'open_fip' [-Wmissing-prototypes]
114 | int open_fip(const uintptr_t spec)
| ^~~~~~~~
plat/st/common/bl2_io_storage.c:119:5: warning: no previous prototype
for 'open_storage' [-Wmissing-prototypes]
119 | int open_storage(const uintptr_t spec)
| ^~~~~~~~~~~~
Add missing stm32mp_io_storage.h header include, where those functions
prototypes are defined.
Olivier Deprez [Fri, 6 May 2022 09:52:55 +0000 (11:52 +0200)]
Merge changes from topic "ja/boot_protocol" into integration
* changes:
fix(sptool): update Optee FF-A manifest
feat(sptool): delete c version of the sptool
feat(sptool): use python version of sptool
feat(sptool): python version of the sptool
refactor(sptool): use SpSetupActions in sp_mk_generator.py
feat(sptool): add python SpSetupActions framework
fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1
Enable ARM_XLAT_TABLES_LIB_V1 as ZynqMP is using
v1 library of translation tables.
With upstream patch d323af9e3d903d981b42f954844a95a6bfef91ab,
the usage of MAP_REGION_FLAT is referring to definition in file
include/lib/xlat_tables/xlat_tables_v2.h but while preparing
xlat tables in lib/xlat_tables/xlat_tables_common.c it is referring
to include/lib/xlat_tables/xlat_tables.h which is v1 xlat tables.
Also, ZynqMP was using v1 so defined ARM_XLAT_TABLES_LIB_V1 to
use v1 xlat tables everywhere.
This fixes the issue of xlat tables failures as it takes v2
library mmap_region structure in some files and v1 in other
files.
projects / arm-tf.git / log