From: Sean Anderson Date: Mon, 26 Oct 2020 01:46:56 +0000 (-0400) Subject: riscv: Move Andes PLMT driver to drivers/timer X-Git-Tag: baikal/mips/sdk5.9~152^2~3 X-Git-Url: https://git.baikalelectronics.ru/?a=commitdiff_plain;h=b1ef248b2f59e689fde5ce59e076356f667d3736;p=uboot.git riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Reviewed-by: Rick Chen --- diff --git a/MAINTAINERS b/MAINTAINERS index fc4fad46ee..5d022352c4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -938,6 +938,7 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git F: arch/riscv/ F: cmd/riscv/ +F: drivers/timer/andes_plmt_timer.c F: tools/prelink-riscv.c RISC-V KENDRYTE diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 756047636d..30b05408b1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -170,13 +170,6 @@ config ANDES_PLIC The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. -config ANDES_PLMT - bool - depends on RISCV_MMODE || SPL_RISCV_MMODE - help - The Andes PLMT block holds memory-mapped mtime register - associated with timer tick. - config SYS_MALLOC_F_LEN default 0x1000 diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 10ac5b06d3..12c14f2019 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -13,7 +13,6 @@ obj-y += cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o -obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c deleted file mode 100644 index cec86718c7..0000000000 --- a/arch/riscv/lib/andes_plmt.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2019, Rick Chen - * Copyright (C) 2020, Sean Anderson - * - * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT). - * The PLMT block holds memory-mapped mtime register - * associated with timer tick. - */ - -#include -#include -#include -#include -#include - -/* mtime register */ -#define MTIME_REG(base) ((ulong)(base)) - -static u64 andes_plmt_get_count(struct udevice *dev) -{ - return readq((void __iomem *)MTIME_REG(dev->priv)); -} - -static const struct timer_ops andes_plmt_ops = { - .get_count = andes_plmt_get_count, -}; - -static int andes_plmt_probe(struct udevice *dev) -{ - dev->priv = dev_read_addr_ptr(dev); - if (!dev->priv) - return -EINVAL; - - return timer_timebase_fallback(dev); -} - -static const struct udevice_id andes_plmt_ids[] = { - { .compatible = "riscv,plmt0" }, - { } -}; - -U_BOOT_DRIVER(andes_plmt) = { - .name = "andes_plmt", - .id = UCLASS_TIMER, - .of_match = andes_plmt_ids, - .ops = &andes_plmt_ops, - .probe = andes_plmt_probe, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index f8fa4aa71f..6b8e4c9dc0 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -53,6 +53,13 @@ config ALTERA_TIMER Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ANDES_PLMT + bool + depends on RISCV_MMODE || SPL_RISCV_MMODE + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + config ARC_TIMER bool "ARC timer support" depends on TIMER && ARC && CLK diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 3a4d74b996..dd4f9cc1d4 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -5,6 +5,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o +obj-$(CONFIG_ANDES_PLMT) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o diff --git a/drivers/timer/andes_plmt_timer.c b/drivers/timer/andes_plmt_timer.c new file mode 100644 index 0000000000..cec86718c7 --- /dev/null +++ b/drivers/timer/andes_plmt_timer.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Rick Chen + * Copyright (C) 2020, Sean Anderson + * + * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT). + * The PLMT block holds memory-mapped mtime register + * associated with timer tick. + */ + +#include +#include +#include +#include +#include + +/* mtime register */ +#define MTIME_REG(base) ((ulong)(base)) + +static u64 andes_plmt_get_count(struct udevice *dev) +{ + return readq((void __iomem *)MTIME_REG(dev->priv)); +} + +static const struct timer_ops andes_plmt_ops = { + .get_count = andes_plmt_get_count, +}; + +static int andes_plmt_probe(struct udevice *dev) +{ + dev->priv = dev_read_addr_ptr(dev); + if (!dev->priv) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + +static const struct udevice_id andes_plmt_ids[] = { + { .compatible = "riscv,plmt0" }, + { } +}; + +U_BOOT_DRIVER(andes_plmt) = { + .name = "andes_plmt", + .id = UCLASS_TIMER, + .of_match = andes_plmt_ids, + .ops = &andes_plmt_ops, + .probe = andes_plmt_probe, + .flags = DM_FLAG_PRE_RELOC, +};