From: Soby Mathew <soby.mathew@arm.com>
Date: Mon, 22 Sep 2014 11:15:26 +0000 (+0100)
Subject: Optimize barrier usage during Cortex-A57 power down
X-Git-Tag: baikal/aarch64/sdk5.9~3476^2~1
X-Git-Url: https://git.baikalelectronics.ru/?a=commitdiff_plain;h=b1a9631d8110a2bcd458ec5809b50d5263a200ef;p=arm-tf.git

Optimize barrier usage during Cortex-A57 power down

This the patch replaces the DSB SY with DSB ISH
after disabling L2 prefetches during the Cortex-A57
power down sequence.

Change-Id: I048d12d830c1b974b161224eff079fb9f8ecf52d
---

diff --git a/lib/cpus/aarch64/cortex_a57.S b/lib/cpus/aarch64/cortex_a57.S
index e7774974a..c2e11bd93 100644
--- a/lib/cpus/aarch64/cortex_a57.S
+++ b/lib/cpus/aarch64/cortex_a57.S
@@ -57,7 +57,7 @@ func cortex_a57_disable_l2_prefetch
 	bic	x0, x0, x1
 	msr	CPUECTLR_EL1, x0
 	isb
-	dsb	sy
+	dsb	ish
 	ret
 
 	/* ---------------------------------------------