From: Marek Vasut Date: Wed, 31 May 2023 18:24:34 +0000 (+0200) Subject: ARM: rmobile: Factor out common R-Car V3M/V3H board code X-Git-Tag: baikal/mips/sdk6.2~4^2~3^2~102^2~22^2~6 X-Git-Url: https://git.baikalelectronics.ru/?a=commitdiff_plain;h=a9d0c4ba579622d7797bcce6ddc42bffb64d33f7;p=uboot.git ARM: rmobile: Factor out common R-Car V3M/V3H board code Pull common board initialization code from V3M Eagle board into rcar-common/v3-common.c so it can be re-used by other V3M/V3H boards. Signed-off-by: Marek Vasut --- diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile index 062c46ba24..9fb6a7c0f0 100644 --- a/board/renesas/eagle/Makefile +++ b/board/renesas/eagle/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_SPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := eagle.o ../rcar-common/common.o +obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c deleted file mode 100644 index e9e8059ef6..0000000000 --- a/board/renesas/eagle/eagle.c +++ /dev/null @@ -1,70 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board/renesas/eagle/eagle.c - * This file is Eagle board support. - * - * Copyright (C) 2017 Marek Vasut - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define CPGWPR 0xE6150900 -#define CPGWPCR 0xE6150904 - -/* PLL */ -#define PLL0CR 0xE61500D8 -#define PLL0_STC_MASK 0x7F000000 -#define PLL0_STC_OFFSET 24 - -#define CLK2MHZ(clk) (clk / 1000 / 1000) -void s_init(void) -{ - struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; - struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; - u32 stc; - - /* Watchdog init */ - writel(0xA5A5A500, &rwdt->rwtcsra); - writel(0xA5A5A500, &swdt->swtcsra); - - /* CPU frequency setting. Set to 0.8GHz */ - stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET; - clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); -} - -int board_early_init_f(void) -{ - /* Unlock CPG access */ - writel(0xA5A5FFFF, CPGWPR); - writel(0x5A5A0000, CPGWPCR); - - return 0; -} - -int board_init(void) -{ - return 0; -} diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/rcar-common/v3-common.c new file mode 100644 index 0000000000..be8be0cb16 --- /dev/null +++ b/board/renesas/rcar-common/v3-common.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2023 Marek Vasut + */ + +#include +#include +#include + +#define CPGWPR 0xE6150900 +#define CPGWPCR 0xE6150904 + +/* PLL */ +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_OFFSET 24 + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 0.8GHz */ + stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); +} + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0xA5A5FFFF, CPGWPR); + writel(0x5A5A0000, CPGWPCR); + + return 0; +} + +int board_init(void) +{ + return 0; +}