From: Paweł Anikiel <pan@semihalf.com>
Date: Tue, 21 Feb 2023 15:17:04 +0000 (+0100)
Subject: arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
X-Git-Tag: baikal/mips/sdk5.8.2~5^2~35^2~2
X-Git-Url: https://git.baikalelectronics.ru/?a=commitdiff_plain;h=46e42ed470a69222c4e2ba9b364cd556c013b80f;p=uboot.git

arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi

This file is included by the different chameleonv3 variants. Change the
name to .dtsi.

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
deleted file mode 100644
index 988cc44543..0000000000
--- a/arch/arm/dts/socfpga_arria10_chameleonv3.dts
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2022 Google LLC
- */
-/dts-v1/;
-#include "socfpga_arria10_mercury_aa1.dtsi"
-
-/ {
-	model = "Google Chameleon V3";
-	compatible = "google,chameleon-v3",
-		     "altr,socfpga-arria10", "altr,socfpga";
-
-	aliases {
-		serial0 = &uart0;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-	};
-};
-
-&gmac0 {
-	status = "okay";
-};
-
-&gpio0 {
-	status = "okay";
-};
-
-&gpio1 {
-	status = "okay";
-};
-
-&gpio2 {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-
-	ssm2603: ssm2603@1a {
-		compatible = "adi,ssm2603";
-		reg = <0x1a>;
-	};
-};
-
-&i2c1 {
-	status = "okay";
-
-	u80: u80@21 {
-		compatible = "nxp,pca9535";
-		reg = <0x21>;
-		gpio-controller;
-		#gpio-cells = <2>;
-
-		gpio-line-names =
-			"SOM_AUD_MUTE",
-			"DP1_OUT_CEC_EN",
-			"DP2_OUT_CEC_EN",
-			"DP1_SOM_PS8469_CAD",
-			"DPD_SOM_PS8469_CAD",
-			"DP_OUT_PWR_EN",
-			"STM32_RST_L",
-			"STM32_BOOT0",
-
-			"FPGA_PROT",
-			"STM32_FPGA_COMM0",
-			"TP119",
-			"TP120",
-			"TP121",
-			"TP122",
-			"TP123",
-			"TP124";
-	};
-};
-
-&mmc {
-	status = "okay";
-};
-
-&uart0 {
-	status = "okay";
-};
-
-&uart1 {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-	dr_mode = "host";
-};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
new file mode 100644
index 0000000000..988cc44543
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+	model = "Google Chameleon V3";
+	compatible = "google,chameleon-v3",
+		     "altr,socfpga-arria10", "altr,socfpga";
+
+	aliases {
+		serial0 = &uart0;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+	};
+};
+
+&gmac0 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	ssm2603: ssm2603@1a {
+		compatible = "adi,ssm2603";
+		reg = <0x1a>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+
+	u80: u80@21 {
+		compatible = "nxp,pca9535";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio-line-names =
+			"SOM_AUD_MUTE",
+			"DP1_OUT_CEC_EN",
+			"DP2_OUT_CEC_EN",
+			"DP1_SOM_PS8469_CAD",
+			"DPD_SOM_PS8469_CAD",
+			"DP_OUT_PWR_EN",
+			"STM32_RST_L",
+			"STM32_BOOT0",
+
+			"FPGA_PROT",
+			"STM32_FPGA_COMM0",
+			"TP119",
+			"TP120",
+			"TP121",
+			"TP122",
+			"TP123",
+			"TP124";
+	};
+};
+
+&mmc {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+	dr_mode = "host";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
index 5f40af6eb9..bef0280212 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
@@ -2,4 +2,4 @@
 /*
  * Copyright 2022 Google LLC
  */
-#include "socfpga_arria10_chameleonv3.dts"
+#include "socfpga_arria10_chameleonv3.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
index 5f40af6eb9..bef0280212 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
@@ -2,4 +2,4 @@
 /*
  * Copyright 2022 Google LLC
  */
-#include "socfpga_arria10_chameleonv3.dts"
+#include "socfpga_arria10_chameleonv3.dtsi"