From: Belsare, Akshay <akshay.belsare@amd.com>
Date: Mon, 6 Mar 2023 09:38:54 +0000 (+0530)
Subject: docs(zynqmp): add ddr address usage
X-Git-Tag: baikal/aarch64/sdk5.10~1^2~168^2
X-Git-Url: https://git.baikalelectronics.ru/?a=commitdiff_plain;h=2b932f83db215dec06336e7d8c8b68f5aa558b6f;p=arm-tf.git

docs(zynqmp): add ddr address usage

Update documentation for TF-A DDR address range usage when the FSBL is
run on RPU instead of APU.

Change-Id: I223d67c35ac9ce3384820531a7453d3b32a1eb58
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
---

diff --git a/docs/plat/xilinx-zynqmp.rst b/docs/plat/xilinx-zynqmp.rst
index f98106237..81f4fbecc 100644
--- a/docs/plat/xilinx-zynqmp.rst
+++ b/docs/plat/xilinx-zynqmp.rst
@@ -76,6 +76,18 @@ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
 	ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> \
 	XILINX_OF_BOARD_DTB_ADDR=<DTB address> bl31
 
+DDR Address Range Usage
+-----------------------
+
+When FSBL runs on RPU and TF-A is to be placed in DDR address range,
+then the user needs to make sure that the DDR address is beyond 256KB.
+In the RPU view, the first 256 KB is TCM memory.
+
+For this use case, with the minimum base address in DDR for TF-A,
+the build command example is;
+
+make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
+	ZYNQMP_ATF_MEM_BASE=0x40000 ZYNQMP_ATF_MEM_SIZE=<size>
 
 FSBL->TF-A Parameter Passing
 ----------------------------