fix(versal-net): add default values for silicon

Add missing default value for silicon.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: Iac7d4db17a29a148298e9e3bd3eb3f74cafe7bc1

diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c
index 97080e91ee908179638c2280b880aaacf0474a84..c9942d6a564c79d460eb1675113c863dda17d16d 100644 (file)
--- a/plat/xilinx/versal_net/bl31_versal_net_setup.c
+++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -88,6 +88,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
                uart_clock = 25000000;
                break;
        case VERSAL_NET_SILICON:
+               cpu_clock = 100000000;
+               uart_clock = 100000000;
+               break;
        default:
                panic();
        }