Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194

This patch fixes the SE clock ID being used for Tegra186 and Tegra194
SoCs. Previous assumption, that both SoCs use the same clock ID, was
incorrect.

Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
index a0d02c94905e705da596942b1e7c4615351456c6..401a07a24131035cc0d61edfa97529ca0d94d47f 100644 (file)
--- a/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
+++ b/plat/nvidia/tegra/include/drivers/bpmp_ipc.h
@@ -18,11 +18,6 @@
 #define TEGRA_RESET_ID_XUSB_PADCTL     U(114)
 #define TEGRA_RESET_ID_GPCDMA          U(70)
 
-/**
- * Clock identifier for the SE device
- */
-#define TEGRA_CLK_SE        U(124)
-
 /**
  * Function to initialise the IPC with the bpmp
  */

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index 3d037e13497981d312475483fc4b4af35aa8dcdd..56157e2deb9ee797af6ddb82a52dddf356068907 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -72,6 +72,12 @@
 
 #define TEGRA186_SEC_IRQ_TARGET_MASK   U(0xF3) /* 4 A57 - 2 Denver */
 
+/*******************************************************************************
+ * Clock identifier for the SE device
+ ******************************************************************************/
+#define TEGRA186_CLK_SE                        U(103)
+#define TEGRA_CLK_SE                   TEGRA186_CLK_SE
+
 /*******************************************************************************
  * Tegra Miscellanous register constants
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index e262c6a9be4477b753c7a5fff194d27af86071f5..7fd97785e8743144545c5f9f5524600d9b790793 100644 (file)
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -42,6 +42,12 @@
 
 #define TEGRA194_SEC_IRQ_TARGET_MASK   U(0xFF) /* 8 Carmel */
 
+/*******************************************************************************
+ * Clock identifier for the SE device
+ ******************************************************************************/
+#define TEGRA194_CLK_SE                        U(124)
+#define TEGRA_CLK_SE                   TEGRA194_CLK_SE
+
 /*******************************************************************************
  * Tegra Miscellanous register constants
  ******************************************************************************/

diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index a0879cc0d071a36d85a925a779348a9df2c655c6..f034bdb87dac47fe81f3c1bf189c429666764f26 100644 (file)
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -294,7 +294,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
                assert(tegra_bpmp_ipc_init() == 0);
 
                /* Enable SE clock */
-               ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+               ret = tegra_bpmp_ipc_enable_clock(TEGRA186_CLK_SE);
                if (ret != 0) {
                        ERROR("Failed to enable clock\n");
                        return ret;
@@ -319,7 +319,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
                memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
                         (uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
 
-               ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+               ret = tegra_bpmp_ipc_disable_clock(TEGRA186_CLK_SE);
                if (ret != 0) {
                        ERROR("Failed to disable clock\n");
                        return ret;

diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
index 0069e3f3b1d3e5d1cbbca1794e7953a59425a6d9..ccdc94d130b6f45bb8f908e8c6bc9005c1006d97 100644 (file)
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -459,7 +459,7 @@ int32_t tegra_se_suspend(void)
        assert(tegra_bpmp_ipc_init() == 0);
 
        /* Enable SE clock before SE context save */
-       ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+       ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE);
        assert(ret == 0);
 
        /* save SE registers */
@@ -475,7 +475,7 @@ int32_t tegra_se_suspend(void)
        }
 
        /* Disable SE clock after SE context save */
-       ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+       ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE);
        assert(ret == 0);
 
        return ret;
@@ -492,7 +492,7 @@ void tegra_se_resume(void)
        assert(tegra_bpmp_ipc_init() == 0);
 
        /* Enable SE clock before SE context restore */
-       ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+       ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE);
        assert(ret == 0);
 
        /*
@@ -507,6 +507,6 @@ void tegra_se_resume(void)
        mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
 
        /* Disable SE clock after SE context restore */
-       ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+       ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE);
        assert(ret == 0);
 }

diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index 7af3b325ddfc3077994f70b36d0ab1e561fac1f1..3c91af4bc74ed2b9742a517d857a625cb29c37c2 100644 (file)
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -304,7 +304,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
                assert(ret == 0);
 
                /* Enable SE clock before SE context save */
-               ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+               ret = tegra_bpmp_ipc_enable_clock(TEGRA194_CLK_SE);
                assert(ret == 0);
 
                /*
@@ -330,7 +330,7 @@ int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_sta
                       src_len_in_bytes);
 
                /* Disable SE clock after SE context save */
-               ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+               ret = tegra_bpmp_ipc_disable_clock(TEGRA194_CLK_SE);
                assert(ret == 0);
        }