fix(errata): workaround for Cortex-A510 erratum 2041909

Cortex-A510 erratum 2041909 is a Cat B erratum that applies to revision
r0p2 and is fixed in r0p3. It is also present in r0p0 and r0p1 but there
is no workaround in these revisions.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN2397239

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I7b1498faa0c79488dee0d11d07f6e9f58144e298

diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 95d43c4eaf5b725efaa4a8e3d5b49c3740ee3e81..71208a8fd2370ad863062714a3651d614d03557a 100644 (file)
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -488,6 +488,11 @@ For Cortex-A510, the following errata build flags are defined :
    Cortex-A510 CPU. This needs to be enabled only for revisions r0p0, r0p1 and
    r0p2, it is fixed in r0p3.
 
+-  ``ERRATA_A510_2041909``: This applies errata 2041909 workaround to
+   Cortex-A510 CPU. This needs to be enabled only for revision r0p2 and is fixed
+   in r0p3. The issue is also present in r0p0 and r0p1 but there is no
+   workaround for those revisions.
+
 DSU Errata Workarounds
 ----------------------
 

diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index 3bf080f633fe13fca21de534614ea4c634da79b8..c288cb23d26df96452430a874d3101ad615e8e36 100644 (file)
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -110,6 +110,49 @@ func check_errata_2042739
        b       cpu_rev_var_ls
 endfunc check_errata_2042739
 
+       /* --------------------------------------------------
+        * Errata Workaround for Cortex-A510 Errata #2041909.
+        * This applies only to revision r0p2 and it is fixed in
+        * r0p3. The issue is also present in r0p0 and r0p1 but
+        * there is no workaround in those revisions.
+        * x0: variant[4:7] and revision[0:3] of current cpu.
+        * Shall clobber: x0, x1, x2, x17
+        * --------------------------------------------------
+        */
+func errata_cortex_a510_2041909_wa
+       /* Check workaround compatibility. */
+       mov     x17, x30
+       bl      check_errata_2041909
+       cbz     x0, 1f
+
+       /* Apply workaround */
+       mov     x0, xzr
+       msr     S3_6_C15_C4_0, x0
+       isb
+
+       mov     x0, #0x8500000
+       msr     S3_6_C15_C4_2, x0
+
+       mov     x0, #0x1F700000
+       movk    x0, #0x8, lsl #32
+       msr     S3_6_C15_C4_3, x0
+
+       mov     x0, #0x3F1
+       movk    x0, #0x110, lsl #16
+       msr     S3_6_C15_C4_1, x0
+       isb
+
+1:
+       ret     x17
+endfunc errata_cortex_a510_2041909_wa
+
+func check_errata_2041909
+       /* Applies only to revision r0p2 */
+       mov     x1, #0x02
+       mov     x2, #0x02
+       b       cpu_rev_var_range
+endfunc check_errata_2041909
+
        /* ----------------------------------------------------
         * HW will do the cache maintenance while powering down
         * ----------------------------------------------------
@@ -143,6 +186,7 @@ func cortex_a510_errata_report
        report_errata ERRATA_A510_1922240, cortex_a510, 1922240
        report_errata ERRATA_A510_2288014, cortex_a510, 2288014
        report_errata ERRATA_A510_2042739, cortex_a510, 2042739
+       report_errata ERRATA_A510_2041909, cortex_a510, 2041909
 
        ldp     x8, x30, [sp], #16
        ret
@@ -175,6 +219,11 @@ func cortex_a510_reset_func
        bl      errata_cortex_a510_2042739_wa
 #endif
 
+#if ERRATA_A510_2041909
+       mov     x0, x18
+       bl      errata_cortex_a510_2041909_wa
+#endif
+
        ret     x19
 endfunc cortex_a510_reset_func
 

diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 53f5e746325fbdee31aac37385d4805d60327978..107753e0fd191f4442671b7c93f7b0984290bd34 100644 (file)
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -543,6 +543,11 @@ ERRATA_A510_2288014        ?=0
 # to revisions r0p0, r0p1 and r0p2 of the Cortex-A510 cpu and is fixed in r0p3.
 ERRATA_A510_2042739    ?=0
 
+# Flag to apply erratum 2041909 workaround during reset. This erratum applies
+# to revision r0p2 of the Cortex-A510 cpu and is fixed in r0p3. The issue is
+# present in r0p0 and r0p1 but there is no workaround for those revisions.
+ERRATA_A510_2041909    ?=0
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953      ?=0
@@ -1012,6 +1017,10 @@ $(eval $(call add_define,ERRATA_A510_2288014))
 $(eval $(call assert_boolean,ERRATA_A510_2042739))
 $(eval $(call add_define,ERRATA_A510_2042739))
 
+# Process ERRATA_A510_2041909 flag
+$(eval $(call assert_boolean,ERRATA_A510_2041909))
+$(eval $(call add_define,ERRATA_A510_2041909))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))