fdts: a5ds: Fix for the system timer issue.

A5DS FPGA system timer clock frequency is 7.5Mhz.
The dt is file updated inline with the hardware
clock frequency.

Change-Id: I3f6c2e0d4a7b293175a42cf398a8730448504af9
Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com>

diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts
index 7334c455990c4c9c3a9d68232a7a5bb8571173b5..c6f5be6fa8c825a913e2282a72ddccef71bf5579 100644 (file)
--- a/fdts/a5ds.dts
+++ b/fdts/a5ds.dts
@@ -128,7 +128,7 @@
                #size-cells = <1>;
                ranges;
                reg = <0x1a040000 0x1000>;
-               clock-frequency = <50000000>;
+               clock-frequency = <7500000>;
 
                frame@1a050000 {
                        frame-number = <0>;