* Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
* Alexey.Malahov <alexey.malahov@baikalelectronics.ru>
* Ekaterina.Skachko <ekaterina.skachko@baikalelectronics.ru>
+ * Danila Sharikov <danila.sharikov@baikalelectronics.ru>
*
- * Copyright (C) 2013-2021 Baikal Electronics JSC
+ * Copyright (C) 2013-2023 Baikal Electronics JSC
*/
#ifndef __CONFIG_BAIKAL_MIPS_H
*/
#ifndef __ASSEMBLER__
extern unsigned long baikal_clk_freq;
-#define CONFIG_SYS_MIPS_TIMER_FREQ (baikal_clk_freq / 2)
+#define CONFIG_SYS_MIPS_TIMER_FREQ (baikal_clk_freq / 2)
#endif
/*
* U-Boot initial parameters
*-----------------------------------------------
*/
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) /* 1 MB */
-#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) /* 128 KB */
-#define CONFIG_SYS_BOOTM_LEN 0x01000000
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) /* 128 KB */
/*
*-----------------------------------------------
* SRAM and it variables
*-----------------------------------------------
*/
-#define CONFIG_SRAM_BASE 0xBBF80000
-#define CONFIG_SRAM_SIZE 0x10000
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE)
+/* Moved to baikal_bfk3_defconfig
+#define CONFIG_SRAM_BASE 0xBBF80000
+#define CONFIG_SRAM_SIZE 0x10000
+#define CUSTOM_SYS_INIT_SP_ADDR 0xBBF90000 (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE)
+*/
/*
*-----------------------------------------------
* Physical Memory Map
*-----------------------------------------------
*/
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CFG_SYS_SDRAM_BASE 0x80000000
/* Only one bank on lower 512 MB can be reached without MMU */
-#define CONFIG_SYS_SDRAM_SIZE 0x08000000
+#define CFG_SYS_SDRAM_SIZE 0x08000000
/*
*-----------------------------------------------
* Miscellaneous configurable options
*-----------------------------------------------
*/
-/* Console I/O Buffer Size */
-#define CONFIG_SYS_CBSIZE 1024
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE 256
-/* Мax number of command args */
-#define CONFIG_SYS_MAXARGS 16
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 1024
+/* Мax number of command args */
+#define CONFIG_SYS_MAXARGS 16
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
*-----------------------------------------------
#ifndef CONFIG_DM_SERIAL
/* UART pool base address */
-#define BAIKAL_NS16550_BASE 0xBF04A000
+#define BAIKAL_NS16550_BASE 0xBF04A000
/* Register width 4 bytes, little endian */
-#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
/* Use NS16550 UART as Serial device */
-#define CONFIG_SYS_NS16550_SERIAL 1
+#define CONFIG_SYS_NS16550_SERIAL 1
/* UART1 is enable and COM1 Port base */
-#define CONFIG_SYS_NS16550_COM1 (BAIKAL_NS16550_BASE + 0x0000)
-/* UART2 is enable and COM2 Port base */
-#define CONFIG_SYS_NS16550_COM2 (BAIKAL_NS16550_BASE + 0x1000)
+#define CONFIG_SYS_NS16550_COM1 (BAIKAL_NS16550_BASE + 0x0000)
+/* UART2 is enable and COM2 Port base */
+#define CONFIG_SYS_NS16550_COM2 (BAIKAL_NS16550_BASE + 0x1000)
#endif
-/* UART CLK divisor */
-#if defined(CONFIG_BAIKAL_T1)
-#define CONFIG_SYS_NS16550_CLK (7350000) /* 7.35MHZ / DIV=4 */
-#else
-#define CONFIG_SYS_NS16550_CLK (12500000) /* 12.5MHZ / DIV=10 */
-#endif /* CONFIG_BAIKAL_T1 */
-
/*
*-----------------------------------------------
* SPI-flash/Boot controller parameters
*-----------------------------------------------
*/
-#define CONFIG_SYS_FLASH_BASE 0x9C000000
+#define CONFIG_SYS_FLASH_BASE 0x9C000000
/*
*-----------------------------------------------
* Misc parameters
*-----------------------------------------------
*/
-#define MACH_SKIP_L2_BYPASS /* Don't set L2B flag - it cannot be cleared */
-
-#define BAIKAL_CPU_CLK_NAME "cpu_clk"
+#define MACH_SKIP_L2_BYPASS /* Don't set L2B flag - it cannot be cleared */
+#define BAIKAL_CPU_CLK_NAME "cpu_clk"
#endif /* __CONFIG_BAIKAL_MIPS_H */