feat(mt8195): add support for SMC from OP-TEE

- Add MTK_SIP_SMC_FROM_S_EL1_TABLE to handle the SMC call from OP-TEE.
- Register optee SMC ID for EMI MPU.

Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Ming Huang <ming.huang@mediatek.com>
Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com>
Change-Id: I924ea85d29d4113e92d8f3d411c0fb77daa0c205

diff --git a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c
index 794e21ef872a0258aff9909e001d950a1635b631..b6e5a2d92f8c3ea6c5a4aa001e62c64aa024501c 100644 (file)
--- a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c
+++ b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,7 @@
 #include <common/debug.h>
 #include <lib/mmio.h>
 #include <emi_mpu.h>
+#include <mtk_sip_svc.h>
 
 #if ENABLE_EMI_MPU_SW_LOCK
 static unsigned char region_lock_state[EMI_MPU_REGION_NUM];
@@ -17,6 +18,7 @@ static unsigned char region_lock_state[EMI_MPU_REGION_NUM];
 #define EMI_MPU_END_MASK               (0x00FFFFFF)
 #define EMI_MPU_APC_SW_LOCK_MASK       (0x00FFFFFF)
 #define EMI_MPU_APC_HW_LOCK_MASK       (0x80FFFFFF)
+#define MPU_PHYSICAL_ADDR_SHIFT_BITS   (16)
 
 static int _emi_mpu_set_protection(unsigned int start, unsigned int end,
                                        unsigned int apc)
@@ -139,7 +141,7 @@ void emi_mpu_init(void)
        /* Forbidden All */
        region_info.start = 0x40000000ULL;      /* dram base addr */
        region_info.end = 0x1FFFF0000ULL;
-       region_info.region = 4;
+       region_info.region = 5;
        SET_ACCESS_PERMISSION(region_info.apc, 1,
                              FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
                              FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
@@ -149,3 +151,42 @@ void emi_mpu_init(void)
 
        dump_emi_mpu_regions();
 }
+
+static inline uint64_t get_decoded_phys_addr(uint64_t addr)
+{
+       return (addr << MPU_PHYSICAL_ADDR_SHIFT_BITS);
+}
+
+static inline uint32_t get_decoded_zone_id(uint32_t info)
+{
+       return ((info & 0xFFFF0000) >> MPU_PHYSICAL_ADDR_SHIFT_BITS);
+}
+
+int32_t emi_mpu_sip_handler(uint64_t encoded_addr, uint64_t zone_size, uint64_t zone_info)
+{
+       uint64_t phys_addr = get_decoded_phys_addr(encoded_addr);
+       struct emi_region_info_t region_info;
+       enum MPU_REQ_ORIGIN_ZONE_ID zone_id = get_decoded_zone_id(zone_info);
+
+       INFO("encoded_addr = 0x%lx, zone_size = 0x%lx, zone_info = 0x%lx\n",
+            encoded_addr, zone_size, zone_info);
+
+       if (zone_id != MPU_REQ_ORIGIN_TEE_ZONE_SVP) {
+               ERROR("Invalid param %s, %d\n", __func__, __LINE__);
+               return MTK_SIP_E_INVALID_PARAM;
+       }
+
+       /* SVP DRAM */
+       region_info.start = phys_addr;
+       region_info.end = phys_addr + zone_size;
+       region_info.region = 4;
+       SET_ACCESS_PERMISSION(region_info.apc, 1,
+                             FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+                             FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+                             FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+                             FORBIDDEN, FORBIDDEN, FORBIDDEN, SEC_RW);
+
+       emi_mpu_set_protection(&region_info);
+
+       return 0;
+}

diff --git a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.h b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.h
index 415146ece868c1d0ac525715baac03f2c8aa82a9..83bd6dee6e2e9f28d465de4f35dbfff4a4059c5c 100644 (file)
--- a/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.h
+++ b/plat/mediatek/mt8195/drivers/emi_mpu/emi_mpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -93,6 +93,15 @@ struct emi_region_info_t {
        unsigned int apc[EMI_MPU_DGROUP_NUM];
 };
 
+enum MPU_REQ_ORIGIN_ZONE_ID {
+       MPU_REQ_ORIGIN_TEE_ZONE_SVP = 0,
+       MPU_REQ_ORIGIN_TEE_ZONE_TUI = 1,
+       MPU_REQ_ORIGIN_TEE_ZONE_WFD = 2,
+       MPU_REQ_ORIGIN_TEE_ZONE_MAX = 3,
+       MPU_REQ_ORIGIN_ZONE_INVALID = 0x7FFFFFFF,
+};
+
 void emi_mpu_init(void);
+int32_t emi_mpu_sip_handler(uint64_t encoded_addr, uint64_t zone_size, uint64_t zone_info);
 
 #endif

diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
index 1cdd622983f8ec989dcfe1a3383ebea994e936d2..2debeffcd58a3e4ffd1f7a7b139ec182e398777c 100644 (file)
--- a/plat/mediatek/mt8195/plat_sip_calls.c
+++ b/plat/mediatek/mt8195/plat_sip_calls.c
@@ -1,11 +1,12 @@
 /*
- * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2020-2023, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <common/debug.h>
 #include <common/runtime_svc.h>
+#include <emi_mpu.h>
 #include <mt_dp.h>
 #include <mt_spm.h>
 #include <mt_spm_vcorefs.h>
@@ -27,6 +28,11 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
        uint32_t ret_val;
 
        switch (smc_fid) {
+       case MTK_SIP_TEE_MPU_PERM_SET_AARCH64:
+       case MTK_SIP_TEE_MPU_PERM_SET_AARCH32:
+               ret = emi_mpu_sip_handler(x1, x2, x3);
+               SMC_RET2(handle, ret, ret_val);
+               break;
        case MTK_SIP_DP_CONTROL_AARCH32:
        case MTK_SIP_DP_CONTROL_AARCH64:
                ret = dp_secure_handler(x1, x2, &ret_val);