plat: marvell: armada: a8k: check CCU window state before loading MSS BL2

Make sure the current CCU window is not in use before adding
a new address map during MSS BL2 image load preparations.
At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is
added to MSS BL2 stage initialization, the DDR entry will be destroyed
and lead to the system hang.

Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
index cdbae9df187a3c776ecdb1a0e7dced1bb6e16b13..c2cd933578ba0a5fbf2b58fca205be2b2d3d4688 100644 (file)
--- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
@@ -63,10 +63,15 @@ static int bl2_plat_mmap_init(void)
         * Do not touch CCU window 0,
         * it's used for the internal registers access
         */
-       for (cfg_idx = 0, win_id = 1; cfg_idx < cfg_num; cfg_idx++, win_id++) {
+       for (cfg_idx = 0, win_id = 1;
+            (win_id < MVEBU_CCU_MAX_WINS) && (cfg_idx < cfg_num); win_id++) {
+               /* Skip already enabled CCU windows */
+               if (ccu_is_win_enabled(MVEBU_AP0, win_id))
+                       continue;
                /* Enable required CCU windows */
                ccu_win_check(&ccu_mem_map[cfg_idx]);
                ccu_enable_win(MVEBU_AP0, &ccu_mem_map[cfg_idx], win_id);
+               cfg_idx++;
        }
 
        /* Config address for each cp other than cp0 */