drm/i915/gen11: Wa_1408615072/Wa_1407596294 should be on GT list

commit 63e082088ae8d862ebe2221e08765d4083984204 upstream.

The UNSLICE_UNIT_LEVEL_CLKGATE register programmed by this workaround
has 'BUS' style reset, indicating that it does not lose its value on
engine resets.  Furthermore, this register is part of the GT forcewake
domain rather than the RENDER domain, so it should not be impacted by
RCS engine resets.  As such, we should implement this on the GT
workaround list rather than an engine list.

Bspec: 19219
Fixes: e3747f971acc ("drm/i915/gen11: Moving WAs to rcs_engine_wa_init()")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230201222831.608281-2-matthew.d.roper@intel.com
(cherry picked from commit b66c49d467fa66f6f963435804a9e066120996d0)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a821e3d405dbef0e9af9eed175db8b26e96e5764..86621dff868df589fd8b2a918904ab38ff875e36 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1249,6 +1249,13 @@ icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
                    GAMT_CHKN_BIT_REG,
                    GAMT_CHKN_DISABLE_L3_COH_PIPE);
 
+       /*
+        * Wa_1408615072:icl,ehl  (vsunit)
+        * Wa_1407596294:icl,ehl  (hsunit)
+        */
+       wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
+                   VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
+
        /* Wa_1407352427:icl,ehl */
        wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2,
                    PSDUNIT_CLKGATE_DIS);
@@ -2368,13 +2375,6 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS,
                             GEN11_ENABLE_32_PLANE_MODE);
 
-               /*
-                * Wa_1408615072:icl,ehl  (vsunit)
-                * Wa_1407596294:icl,ehl  (hsunit)
-                */
-               wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE,
-                           VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS);
-
                /*
                 * Wa_1408767742:icl[a2..forever],ehl[all]
                 * Wa_1605460711:icl[a0..c0]