Tegra: memctrl_v2: remove non-secure access to TZSRAM memory

This patch removes the memory controller configuration setting, which
allowed non-secure access to the TZSRAM memory.

Change-Id: Ic13645ba6a7694f192565962df40ca4fb8130f23
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 18f33682dde9d24d6d8133b953f8353c6a8fbfb3..5986416e24d857de5a7d10293f8d9ac878a5b4a8 100644 (file)
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -678,13 +678,6 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
             index += 4)
                tegra_mc_write_32(index, 0);
 
-       /*
-        * Allow CPU read/write access to the aperture
-        */
-       tegra_mc_write_32(MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1,
-               TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT |
-               TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT);
-
        /*
         * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
         */

diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index f919ac378e814fa090a81ff0745f2ae713fbe407..8a1dd3f24f23ec36d73859251da5f20cb3e1cd9a 100644 (file)
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -182,8 +182,6 @@
 #define  TZRAM_ENABLE_TZ_LOCK_BIT              (1 << 0)
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0   0x21A0
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1   0x21A4
-#define  TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT   (1 << 25)
-#define  TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT    (1 << 7)
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2   0x21A8
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3   0x21AC
 #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4   0x21B0