clk: qcom: ipq8074: fix NSS port frequency tables

[ Upstream commit 81d4da77d2bc2f7dc7f559121d69d3fa17bc3149 ]

NSS port 5 and 6 frequency tables are currently broken and are causing a
wide ranges of issue like 1G not working at all on port 6 or port 5 being
clocked with 312 instead of 125 MHz as UNIPHY1 gets selected.

So, update the frequency tables with the ones from the downstream QCA 5.4
based kernel which has already fixed this.

Fixes: 34e5b8de3c8f ("clk: qcom: ipq8074: add NSS ethernet port clocks")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220515210048.483898-3-robimarko@gmail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index de48ba7eba3a15676fe69b0d454e13fe22644787..735a1cb59ffa114a5bd76b077223af713a5170ce 100644 (file)
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1788,8 +1788,10 @@ static struct clk_regmap_div nss_port4_tx_div_clk_src = {
 static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
        F(19200000, P_XO, 1, 0, 0),
        F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
+       F(25000000, P_UNIPHY0_RX, 5, 0, 0),
        F(78125000, P_UNIPHY1_RX, 4, 0, 0),
        F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
+       F(125000000, P_UNIPHY0_RX, 1, 0, 0),
        F(156250000, P_UNIPHY1_RX, 2, 0, 0),
        F(312500000, P_UNIPHY1_RX, 1, 0, 0),
        { }
@@ -1828,8 +1830,10 @@ static struct clk_regmap_div nss_port5_rx_div_clk_src = {
 static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
        F(19200000, P_XO, 1, 0, 0),
        F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
+       F(25000000, P_UNIPHY0_TX, 5, 0, 0),
        F(78125000, P_UNIPHY1_TX, 4, 0, 0),
        F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
+       F(125000000, P_UNIPHY0_TX, 1, 0, 0),
        F(156250000, P_UNIPHY1_TX, 2, 0, 0),
        F(312500000, P_UNIPHY1_TX, 1, 0, 0),
        { }
@@ -1867,8 +1871,10 @@ static struct clk_regmap_div nss_port5_tx_div_clk_src = {
 
 static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
        F(19200000, P_XO, 1, 0, 0),
+       F(25000000, P_UNIPHY2_RX, 5, 0, 0),
        F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
        F(78125000, P_UNIPHY2_RX, 4, 0, 0),
+       F(125000000, P_UNIPHY2_RX, 1, 0, 0),
        F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
        F(156250000, P_UNIPHY2_RX, 2, 0, 0),
        F(312500000, P_UNIPHY2_RX, 1, 0, 0),
@@ -1907,8 +1913,10 @@ static struct clk_regmap_div nss_port6_rx_div_clk_src = {
 
 static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
        F(19200000, P_XO, 1, 0, 0),
+       F(25000000, P_UNIPHY2_TX, 5, 0, 0),
        F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
        F(78125000, P_UNIPHY2_TX, 4, 0, 0),
+       F(125000000, P_UNIPHY2_TX, 1, 0, 0),
        F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
        F(156250000, P_UNIPHY2_TX, 2, 0, 0),
        F(312500000, P_UNIPHY2_TX, 1, 0, 0),